EM357-RTR Ember, EM357-RTR Datasheet - Page 50

• Manufacturer Part Number: EM357-RTR
• Description: IC RF TXRX ZIGBEE 192KB 48QFN
• Manufacturer: Ember

Specifications of EM357-RTR

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 5dBm
• Sensitivity: -100dBm
• Voltage - Supply: 2.1 V ~ 3.6 V
• Current - Receiving: 26mA
• Current - Transmitting: 31mA
• Data Interface: PCB, Surface Mount
• Memory Size: 192kB Flash, 12kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 636-1011-2

CSYSPWRUPREQ, CDBGPWRUPREQ, and the corresponding CSYSPWRUPACK and CDBGPWRUPACK are bits in the
debug port’s CTRL/STAT register in the SWJ. For further information on these bits and the operation of the
SWJ-DP please refer to the ARM Debug Interface v5 Architecture Specification (ARM IHI 0031A).
For further power savings when not in deep sleep, the ADC, Timer 1, Timer 2, Serial Controller 1, and Serial
Controller 2 peripherals can be individually disabled through the PERIPHERAL_DISABLE register. Disabling a
peripheral saves power by stopping the clock feeding that peripheral. A peripheral should only be disabled
through the PERIPHERAL_DISABLE register when the peripheral is idle and disabled through the peripheral's
own configuration registers, otherwise undefined behavior may occur. When a peripheral is disabled through
the PERIPHERAL_DISABLE register, all registers associated with that peripheral ignore all subsequent writes,
and subsequent reads return the value seen in the register at the moment the peripheral is disabled.
6.5.1
When in deep sleep the EM35x can be returned to the running state in a number of ways, and the wake
sources are split depending on deep sleep 1 or deep sleep 2.
The following wake sources are available in both deep sleep 1 and 2.
The following sources are only available in deep sleep 1 since the sleep timer is not active in deep sleep 2.
The following source is only available in deep sleep 0 since the SWJ is required to write a memory mapped
register to set this wake source and the SWJ only has access to some registers in deep sleep 0.
The Wakeup Recording module monitors all possible wakeup sources. More than one wakeup source may be
recorded because events are continually being recorded (not just in deep-sleep) and another event may
happen between the first wake event and when the EM35x wakes up.
Deep Sleep 1: The primary deep sleep state. In this state, the core power domain is fully powered down
and the sleep timer is active.
Deep Sleep 2: The same as Deep Sleep 1 except that the sleep timer is inactive to save power. In this
mode the sleep timer cannot wake up the EM35x.
Deep Sleep 0 (also known as Emulated Deep Sleep): The chip emulates a true deep sleep without powering
down the core domain. Instead, the core domain remains powered and all peripherals except the system
debug components (ITM, DWT, FPB, NVIC) are held in reset. The purpose of this sleep state is to allow
EM35x software to perform a deep sleep cycle while maintaining debug configuration such as breakpoints.
Wake on GPIO activity: Wake due to change of state on any GPIO.
Wake on serial controller 1: Wake due to a change of state on GPIO Pin PB2.
Wake on serial controller 2: Wake due to a change of state on GPIO Pin PA2.
Wake on IRQD: Wake due to a change of state on IRQD. Since IRQD can be configured to point to any GPIO,
this wake source is another means of waking on any GPIO activity.
Wake on setting of CDBGPWRUPREQ: Wake due to setting the CDBGPWRUPREQ bit in the debug port in the
SWJ.
Wake on setting of CSYSPWRUPREQ: Wake due to setting the CSYSPWRUPREQ bit in the debug port in the
SWJ.
Wake on sleep timer compare A.
Wake on sleep timer compare B.
Wake on sleep timer wrap.
Wake on write to the WAKE_CORE register bit.
Wake Sources
Final
6-12
EM351 / EM357
120-035X-000G