MC13224V Freescale Semiconductor, MC13224V Datasheet - Page 23

• Manufacturer Part Number: MC13224V
• Description: ZIGBEE PLATFORM 802.15.4 145-LGA
• Manufacturer: Freescale Semiconductor

Specifications of MC13224V

• Frequency: 2.4GHz
• Data Rate - Maximum: 250kbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 4dBm
• Sensitivity: -100dBm
• Voltage - Supply: 2 V ~ 3.6 V
• Current - Receiving: 24mA
• Current - Transmitting: 29mA
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 96kB RAM
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 145-LGA
• Number Of Receivers: 1
• Number Of Transmitters: 1
• Wireless Frequency: 2.4 GHz
• Interface Type: 4-Wire SPI, I2C
• Output Power: 1.5 dBm
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Maximum Supply Current: 31 mA
• Minimum Operating Temperature: - 40 C
• Modulation: OQPSK
• Protocol Supported: 802.15.4
• No. Of Pins: 99
• Supply Voltage Range: 2V To 3.6V
• Operating Temperature Range: -40°C To +125°C
• Msl: MSL 3 - 168 Hours
• A/d Converter: 12 Bits
• No. Of Timers 8/12/16/32 Bits: 0 / 0 / 4 / 0
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.5
The MC1322x provides an Inter-Integrated Circuit (I
data (SDA) and serial clock (SCL), bidirectional serial bus. The I
MC1322x and other devices such as MCUs, serial EEPROM, serial ADC and DAC devices, and LCDs.
The I
additional devices to be connected and still handle system expansion and development. The bus includes
collision detection and arbitration to prevent data corruption if two or more masters attempt to
simultaneously control the I
The I
generated from a prescaler. The prescaler divide ratio can be programmed from 61,440 to 160 (decimal)
which gives a maximum bit clock of 150 kbps.
The I
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2
2
2
C minimizes interconnections between devices and is a synchronous, multi-master bus that allows
C module is driven by the peripheral bus clock (typically 24 MHz) and the SCL bit clock is
C module supports the following features:
Status flags for various flow control and FIFO states
Receiver detects framing errors, start bit error, break characters, parity errors, and overrun errors.
Voting logic for improved noise immunity (16X/8X oversampling)
Maskable interrupt request
Time-out counter, which times out after eight non-present characters
Receiver and transmitter enable/disable
Low-power modes
Baud rate generator to provide any multiple-of-2 baud rate between 1.2 kbaud and 1,843.2 kbaud
Two-wire (SDA and SCL) interface
Multi-master operation
Master or slave mode
Arbitration lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
START and STOP signal generation/detection
Acknowledge bit generation/detection
Bus busy detection
Software-programmable bit clock frequency up to 150 kbps
Software-selectable acknowledge bit
On-chip filtering for spikes on the bus
Inter-Integrated Circuit (I
2
C.
MC1322x Technical Data, Rev. 1.3
2
C) Module
2
C) module for the I
2
C allows for data exchange between the
2
C which is a two-wire, serial
23