KSZ8863FLLI Micrel Inc, KSZ8863FLLI Datasheet - Page 12

• Manufacturer Part Number: KSZ8863FLLI
• Description: IC ETHERNET SWITCH 3PORT 48-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8863FLLI

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3750

Micrel, Inc.
August 2010
Pin Number
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Pin Name
SMRXDV3
SMRXD33/
REFCLKO_3
SMRXD32
SMRXD31
SMRXD30
SMRXC3
GND
VDDC
SCOL3
SCRS3
INTRN
SCL_MDC
SDA_MDIO
SPIQ
Type
Ipu/O
Ipu/O
lpu/O
lpu/O
lpu/O
lpd/O
Gnd
Opu
I/O
I/O
I/O
I/O
I/O
P
(1)
Description
Switch MII/RMII receive data valid
Strap option: Force duplex mode (P1DPX)
PU = port 1 default to full duplex mode if P1ANEN = 1 and auto-
negotiation fails. Force port 1 in full-duplex mode if P1ANEN = 0.
PD = port 1 default to half duplex mode if P1ANEN = 1 and auto-
negotiation fails. Force port 1 in half duplex mode if P1ANEN = 0.
MLL/FLL: Switch MII receive data bit 3/
RLL: Ouput reference clock in RMII mode.
Strap option: enable auto-negotiation on port 2 (P2ANEN)
PU = enable
PD = disable
Switch MII receive data bit 2
Strap option: Force the speed on port 2 (P2SPD)
PU = force port 2 to 100BT if P2ANEN = 0
PD = force port 2 to 10BT if P2ANEN = 0
Switch MII/RMII receive data bit 1
Strap option: Force duplex mode (P2DPX)
PU = port 2 default to full duplex mode if P2ANEN = 1 and auto-negotiation
fails. Force port 2 in full duplex mode if P2ANEN = 0.
PD = Port 2 set to half duplex mode if P2ANEN = 1 and auto-negotiation
fails. Force port 2 in half duplex mode if P2ANEN = 0.
Switch MII/RMII receive data bit 0
Strap option: Force flow control on port 2 (P2FFC)
PU = always enable (force) port 2 flow control feature.
PD = port 2 flow control feature enable is determined by auto- negotiation
result.
Switch MII receive clock.
Output in PHY MII mode
Input in MAC MII mode
Digital ground
1.8V digital core power input from VDDCO (pin 42).
Switch MII collision detect
Switch MII carrier sense
Interrupt
Active Low signal to host CPU to indicate an interrupt status bit is set when
lost link. Refer to register 187 and 188.
SPI slave mode / I
I
MIIM clock input
SPI slave mode: serial data input
I
MIIM: data input/out
Note: an external pull-up is needed on this pin when it is in use.
SPI slave mode: serial data output
Note: an external pull-up is needed on this pin when it is in use.
2
2
C master mode: clock output
C master/slave mode: serial data input/output
12
2
C slave mode: clock input
KSZ8863MLL/FLL/RLL
M9999-081810-1.2