KSZ8863FLLI Micrel Inc, KSZ8863FLLI Datasheet - Page 57

• Manufacturer Part Number: KSZ8863FLLI
• Description: IC ETHERNET SWITCH 3PORT 48-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8863FLLI

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3750

Micrel, Inc.
Note: Bits [2:0] are used for spanning tree support.
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
Note: Registers 19 and 20 (and those corresponding to other ports) serve two purposes:
Associated with the ingress untagged packets, and used for egress tagging.
Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
September 2009
7-0
7-0
Bit
Bit
Bit
Bit
3
2
1
0
7
6
Pressure
Enable
Transmit
Enable
Receive
Enable
Learning
Disable
[15:8]
[7:0]
Port 3 MII
mode
Selection
Self-address
filtering
enable
MACA1
(not for
0x35)
Name
Back
Name
Default Tag
Name
Default Tag
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
= 1, enable port’s half duplex back pressure
= 0, disable port’s half duplex back pressure
= 1, enable packet transmission on the port
= 0, disable packet transmission on the port
= 1, enable packet reception on the port
= 0, disable packet reception on the port
= 1, disable switch address learning capability
= 0, enable switch address learning
Description
Port’s default tag, containing
Description
Port’s default tag, containing
Description
1: Port 3 MII MAC mode
0: Port 3 MII PHY mode
Note: Bit 7 is reserved for port 1 and port 2
=1, enable port 1 self-address filtering MACA1
=0, disable
7-5 : User priority bits
4 : CFI bit
3-0 : VID[11:8]
7-0
: VID[7:0]
57
Default
KSZ8863MLL/FLL/RLL
control is set by
Default
Default
Reg. 6, bit 5.
0
0
0x00
0x01
Default
M9999-091009-1.1
0
1
1
0