KSZ8863FLLI Micrel Inc, KSZ8863FLLI Datasheet - Page 39

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KSZ8863FLLI

Manufacturer Part Number
KSZ8863FLLI
Description
IC ETHERNET SWITCH 3PORT 48-LQFP
Manufacturer
Micrel Inc
Datasheet

Specifications of KSZ8863FLLI

Controller Type
Ethernet Switch Controller
Interface
MII
Voltage - Supply
1.8V, 2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Supplier Unconfirmed, Lead free / RoHS Compliant
Other names
576-3750

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
KSZ8863FLLI
Manufacturer:
Micrel
Quantity:
446
Part Number:
KSZ8863FLLI
Manufacturer:
Micrel Inc
Quantity:
10 000
Part Number:
KSZ8863FLLI
0
Micrel, Inc.
The KSZ8863MLL/FLL/RLL is capable of supporting a SPI bus.
The following is a sample procedure for programming the KSZ8863MLL/FLL/RLL using the SPI bus:
Some of the configuration settings, such as “Aging enable”, “Auto Negotiation Enable”, “Force Speed” and “Power down”
can be programmed after the switch has been started.
The following four figures illustrate the SPI data cycles for “Write”, “Read”, “Multiple Write” and “Multiple Read”. The read
data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is registered on the rising edge of
SPIC.
August 2010
1. At the board level, connect the KSZ8863MLL/FLL/RLL pins as follows:
2. Enable SPI slave mode by setting the KSZ8863MLL/FLL/RLL strap-in pins P2LED[1:0] to “10”.
3. Power up the board and assert reset to the KSZ8863MLL/FLL/RLL.
4. Configure the desired register settings in the KSZ8863MLL/FLL/RLL, using the SPI write or multiple write
5. Read back and verify the register settings in the KSZ8863MLL/FLL/RLL, using the SPI read or multiple read
command.
command.
KSZ8863MLL/FLL/RLL Pin #
39
36
37
38
SPIS_N
SPIC
SPID
SPIQ
X
0
0
READ COMMAND
0
0
KSZ8863MLL/FLL/RLL Signal Name
SPISN
SCL
(SPIC)
SDA
(SPID)
SPIQ
0
0
Figure 10. SPI Write Data Cycle
Figure 11. SPI Read Data Cycle
1
Table 13. SPI Connections
1
A7 A6 A5 A4 A3 A2 A1 A0
READ ADDRESS
39
External Processor Signal Description
SPI Slave Select
SPI Clock
SPI Data
(Master output; Slave input)
SPI Data
(Master input; Slave output)
D7
D6
READ DATA
D5
D4
D3
D2
D1
KSZ8863MLL/FLL/RLL
D0
M9999-081810-1.2

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