KSZ8863FLLI Micrel Inc, KSZ8863FLLI Datasheet - Page 31

• Manufacturer Part Number: KSZ8863FLLI
• Description: IC ETHERNET SWITCH 3PORT 48-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8863FLLI

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3750

Micrel, Inc.
Serial Management Interface (SMI)
The SMI is the KSZ8863MLL/FLL/RLL non-standard MIIM interface that provides access to all KSZ8863MLL/FLL/RLL
configuration registers. This interface allows an external device to completely monitor and control the states of the
KSZ8863MLL/FLL/RLL.
The SMI interface consists of the following:
The following table depicts the SMI frame format.
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register
write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit[3] is
undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read/write operations.
To access the KSZ8863MLL/FLL/RLL registers 0-196 (0x00 – 0xC6), the following applies:
SMI register access is the same as the MIIM register access, except for the register access requirements presented in
this section.
Advanced Switch Functions
Bypass Mode
The KSZ8863MLL/FLL/RLL also offer a by-pass mode which enables system-level power saving. When the CPU
(connected to Port 3) enters a power saving mode of power down or sleeping mode, the CPU can control the pin 24
SMTXER3/MII_LINK_3 which can be tied high so that the KSZ8863MLL/FLL/RLL detect this change and automatically
switches to the by-pass mode in which the switch function between Port1 and Port2 is sustained. In the by-pass mode,
the packets with DA to port 3 will be dropped and by pass the internal buffer memory, make the buffer memory more
efficiency for the data transfer between port 1 and port 2. Specially, the power saving get more in energy detect mode with
the by-pass to be used.
IEEE 802.1Q VLAN Support
The KSZ8863MLL/FLL/RLL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q
specification. KSZ8863MLL/FLL/RLL provides a 16-entries VLAN Table, which converts the 12-bits VLAN ID (VID) to the
4-bits Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID
is used for lookup. In VLAN mode, the lookup process starts with VLAN Table lookup to determine whether the VID is
valid. If the VID is not valid, the packet is dropped and its address is not learned. If the VID is valid, the FID is retrieved for
further lookup. The FID + Destination Address (FID+DA) are used to determine the destination port. The FID + Source
Address (FID+SA) are used for address learning.
August 2010
• A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller to
• Access to all KSZ8863MLL/FLL/RLL configuration registers. Register access includes the Global, Port and Advanced
• PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address;
• Registers are 8 data bits wide.
communicate with the KSZ8863MLL/FLL/RLL device.
Control Registers 0-198 (0x00 – 0xC6), and indirect access to the standard MIIM registers [0:5] and custom MIIM
registers [29, 31].
that is, {PHYAD[2:0], REGAD[4:0]} = bits [7:0] of the 8-bit address.
Read
Write
For read operation, data bits [15:8] are read back as 0’s.
For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
Preamble
32 1’s
32 1’s
Start of
Frame
01
01
Table 9. Serial Management Interface (SMI) Frame Format
Read/Write
OP Code
00
00
PHY
Address
Bits [4:0]
1xRRR
0xRRR
31
REG
Address
Bits [4:0]
RRRRR
RRRRR
TA
Z0
10
Data Bits [15:0]
0000_0000_DDDD_DDDD
xxxx_xxxx_DDDD_DDDD
KSZ8863MLL/FLL/RLL
M9999-081810-1.2
Idle
Z
Z