KSZ8863FLLI Micrel Inc, KSZ8863FLLI Datasheet - Page 78

• Manufacturer Part Number: KSZ8863FLLI
• Description: IC ETHERNET SWITCH 3PORT 48-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8863FLLI

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3750

Micrel, Inc.
Register 194 (0xC2): Insert SRC PVID
Register 195 (0xC3): Power Management and LED Mode
September 2009
7-6
5
4
3
2
1
0
5-4
Bit
Bit
7
6
3
2
Insert SRC
port 1 PVID at
Port 2
Insert SRC
port 1 PVID at
Port 3
Insert SRC
port 2 PVID at
Port 1
Insert SRC
port 2 PVID at
Port 3
Insert SRC
port 3 PVID at
Port 1
Insert SRC
port 3 PVID at
Port 2
CPU interface
Power Down
Switch Power
Down
LED Mode
Selection
LED output
mode
PLL Off Enable
Name
Reserved
Name
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Do not change the default value.
1= insert SRC port 1 PVID for untagged frame at egress
port 2
1= insert SRC port 1 PVID for untagged frame at egress
port 3
1= insert SRC port 2 PVID for untagged frame at egress
port 1
1= insert SRC port 2 PVID for untagged frame at egress
port 3
1= insert SRC port 3 PVID for untagged frame at egress
port 1
1= insert SRC port 3 PVID for untagged frame at egress
port 2
Description
CPU interface clock tree power down enable.
1: Enable
0: Disable
Note: Power save a little bit when MII interface is used and
the traffic is stopped in the power management with normal
mode
Switch clock tree power down enable.
1: Enable
0:Disable
Note: Power save a little bit when MII interface is used and
the traffic is stopped in the power management with normal
mode
00: LED0 -> Link/ACT, LED1-> Speed
01: LED0 -> Link,
10: LED0 -> Link/ACT, LED1 -> Duplex
11: LED0 -> Link,
=1, the internal stretched energy signal from the analog
module will be negated and output to LED1 and the internal
device ready signal will be negated and output to LED0.
=0, the LED1/LED0 pins will indicate the regular LED
outputs.
(Note. This is for debugging purpose.)
=1, PLL power down enable
=0, disable
Note: This bit is used in Energy Detect mode with pin 27
MII_LINK_3 pull-up in the by-pass mode for saving power
LED1 -> ACT
LED1 -> Duplex
78
00
0
0
0
0
0
0
Default
Default
00
0
0
0
0
KSZ8863MLL/FLL/RLL
M9999-091009-1.1