KSZ8863FLLI Micrel Inc, KSZ8863FLLI Datasheet - Page 2

• Manufacturer Part Number: KSZ8863FLLI
• Description: IC ETHERNET SWITCH 3PORT 48-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8863FLLI

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3750

Micrel, Inc.
Features
• Advanced Switch Features
• Comprehensive Configuration Register Access
• QoS/CoS Packet Prioritization Support
• Proven Integrated 3-Port 10/100 Ethernet Switch
August 2010
- IEEE 802.1q VLAN support for up to 16 groups
- VLAN ID tag/untag options, per port basis
- IEEE 802.1p/q tag insertion or removal on a per
- Programmable rate limiting at the ingress and
- Broadcast storm protection with % control
- IEEE 802.1d rapid spanning tree protocol
- tail tag mode (1 byte added before FCS) support
- Bypass feature which Automatically sustains the
- Self-address filtering
- Individual MAC address for port1 and port2
- Support RMII interface and 50 MHz reference
- IGMP snooping (Ipv4) support for multicast
- IPv4/IPv6 QoS support.
- MAC filtering function to forward unknown
- Double-tagging support
- Serial management interface (SMI) to all internal
- MII management (MIIM) interface to PHY
- High speed SPI and I
- I/0 pins strapping and EEPROM to program
- Control registers configurable on the fly (port-
- Per port, 802.1p and DiffServ-based
- Re-mapping of 802.1p priority field per port
- 3rd generation switch with three MACs and two
- Non-blocking switch fabric assures fast packet
(full-range of VLAN IDs)
port basis (egress)
egress on a per port basis
(global and per port basis)
support
at port3 to inform the processor which ingress
port receives the packet and its priority
switch function between Port1 and Port2 when
CPU (Port 3 interface) goes to the sleep mode
clock output
packet Filtering
unicast packets to specified port
registers
registers
registers
selective registers in unmanaged switch mode
priority, 802.1p/d/q, AN…)
basis Four priority levels
PHYs fully compliant with IEEE 802.3u standard
delivery by utilizing an 1K MAC address lookup
table and a store-and-forward architecture
2
C Interface to all internal
2
• Switch Monitoring Features
• Low Power Dissipation
• Industrial Temperature Range: –40
• Available in 48-Pin LQFP, Lead-free package
Applications
• Typical
- Full duplex IEEE 802.3x flow control (PAUSE)
- Half-duplex back pressure flow control
- HP Auto MDI-X for reliable detection of and
- Micre LinkMD
- MII interface supports both MAC mode and PHY
- Comprehensive LED Indicator support for link,
- HBM ESD Rating 6kV
- Port mirroring/monitoring/sniffing: ingress and/or
- MIB counters for fully compliant statistics
- Loopback modes for remote diagnostic of failure
- Full-chip hardware power-down (register
- Full-chip software power-down (register
- Energy-detect mode support
- Dynamic clock tree shutdown feature
- Per port based software power-save on PHY
- Voltages: Single 3.3V supply with internal 1.8V
- Optional 3.3V, 2.5V and 1.8V for VDDIO
- Transceiver power 3.3V for VDDA_3.3
- VoIP Phone
- Set-top/Game Box
- Automotive
- Industrial Control
- IPTV POF
- SOHO Residential Gateway
- Broadband Gateway / Firewall / VPN
- Integrated DSL/Cable Modem
- Wireless LAN access point + gateway
- Standalone 10/100 switch
with force mode option
correction for straight-through and crossover
cables with disable and enable option
permit identification of faulty copper cabling on
Port 2
mode
activity, full/half duplex and 10/100 speed
egress traffic to any port or MII
gathering 34 MIB counters per port
configuration not saved)
configuration not saved)
(idle link detection, register configuration
preserved)
LDO for 3.3V VDDIO
®
TDR-based cable diagnostics
KSZ8863MLL/FLL/RLL
M9999-081810-1.2
o
C to +85
o
C