KSZ8863FLLI Micrel Inc, KSZ8863FLLI Datasheet - Page 13

• Manufacturer Part Number: KSZ8863FLLI
• Description: IC ETHERNET SWITCH 3PORT 48-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8863FLLI

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3750

Micrel, Inc.
August 2010
Pin Number
39
40
41
42
43
44
45
46
Pin Name
SPISN
VDDIO
GND
VDDCO
P1LED1
P1LED0
P2LED1
P2LED0
Type
Ipu/O
Ipd/O
Ipu/O
Ipu/O
Gnd
P
P
I
(1)
Description
Strap option: Force flow control on port 1 (P1FFC)
PU = always enable (force) port 1 flow control feature
PD = port 1 flow control feature enable is determined by auto negotiation
result.
When SPISN is high, the KSZ8863MLL/FLL/RLLis deselected and SPIQ is
held in high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
Note: an external pull-up is needed on this pin when it is in use.
3.3V, 2.5V or 1.8V digital VDD input power supply for IO with well
decoupling capacitors.
Digital ground
1.8V output pin provides power to both VDDA_1.8 and VDDC input pins.
Note: Internally 1.8V LDO regulator input comes from VDDIO. Do not
connect an external power supply to VDDCO pin. The ferrite bead is
requested between analog and digital 1.8V core power.
Port 1 LED Indicators:
Default: Speed (refer to register 195 bit[5:4])
Strap option: Force the speed on port 1 (P1SPD)
PU = force port 1 to 100BT if P1ANEN = 0
PD = force port 1 to 10BT if P1ANEN = 0
Port 1 LED Indicators:
Default: Link/Act. (refer to register 195 bit[5:4])
Strap option: enable auto-negotiation on port 1 (P1ANEN)
PU = enable
PD = disable
Port 2 LED Indicators:
Default: Speed (refer to register 195 bit[5:4])
Strap option: Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to register 195 bit[5:4])
Strap option: Serial bus configuration
Serial bus configuration pins to select mode of access to
KSZ8863MLL/FLL/RLL internal registers.
[P2LED1, P2LED0] = [0, 0] — I
(If EEPROM is not detected, the KSZ8863MLL/FLL/RLL will be configured
with the default values of its internal registers and the values of its strap-in
pins.)
[P2LED1, P2LED0] = [0, 1] — I
The external I
The KSZ8863MLL/FLL/RLL device addresses are:
SPI slave mode: chip select (active low)
1.8V core power voltage output (internal 1.8V LDO regulator output), this
Interface Signals
SPIQ
SCL_MDC
SDA_MDIO
SPISN
13
2
C master will drive the SCL_MDC clock.
Type
O
O
I/O
I
Description
Not used (tri-stated)
I
I
Not used
2
2
C clock
C data I/O
2
2
C master (EEPROM) mode
C slave mode
KSZ8863MLL/FLL/RLL
M9999-081810-1.2