KSZ8863FLLI Micrel Inc, KSZ8863FLLI Datasheet - Page 71

• Manufacturer Part Number: KSZ8863FLLI
• Description: IC ETHERNET SWITCH 3PORT 48-LQFP
• Manufacturer: Micrel Inc

Specifications of KSZ8863FLLI

• Controller Type: Ethernet Switch Controller
• Interface: MII
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant
• Other names: 576-3750

Micrel, Inc.
Registers 118 to 120
Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be
used to pass user defined control and status information between the KSZ8863 and the external processor.
Register 118 (0x76): User Defined Register 1
Register 119 (0x77): User Defined Register 2
Register 120 (0x78): User Defined Register 3
Registers 121 to 131
Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC address
table, and MIB counters.
Register 121 (0x79): Indirect Access Control 0
Register 122 (0x7A): Indirect Access Control 1
Note: A write to register 122 triggers the read/write command. Read or write access is determined by register 121 bit 4.
Register 123 (0x7B): Indirect Data Register 8
September 2009
7-0
7-0
7-0
7-5
3-2
1-0
7-0
6-3
2-0
Bit
Bit
Bit
Bit
Bit
Bit
4
7
UDR1
UDR2
UDR3
Read High /
Write Low
Indirect
Address High
Indirect
Address Low
CPU Read
Status
Indirect Data
[66:64]
Name
Name
Name
Name
Reserved
Table Select
Name
Name
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
Description
Description
Description
Description
Reserved
Do not change the default values.
= 1, read cycle
= 0, write cycle
00 = static MAC address table selected
01 = VLAN table selected
10 = dynamic MAC address table selected
11 = MIB counter selected
Bits [9:8] of indirect address
Description
Bits [7:0] of indirect address
Description
This bit is applicable only for dynamic MAC address table
and MIB counter reads.
= 1, read is still in progress
= 0, read has completed
Reserved
Bits [66:64] of indirect data
71
0000_0000
Default
Default
Default
Default
Default
Default
0x00
0x00
0x00
0000
000
000
00
00
0
0
KSZ8863MLL/FLL/RLL
M9999-091009-1.1