LPC2420FET208,551 NXP Semiconductors, LPC2420FET208,551 Datasheet - Page 2

• Manufacturer Part Number: LPC2420FET208,551
• Description: IC ARM7 MCU 16BIT T208FBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2420FET208,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: EBI/EMI, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 82K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-TFBGA
• Processor Series: LPC2420
• Core: ARM7
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: SPI, I2C, I2S, USB, SSP
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Processor To Be Evaluated: ARM7TDMI-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5216

NXP Semiconductors
LPC2420_60_5
Preliminary data sheet
Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet
DMA, and USB DMA with no contention (LPC2460 only).
EMC provides support for asynchronous static memory devices such as RAM, ROM
and flash, as well as dynamic memories such as single data rate SDRAM.
Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts.
General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP,
I
Serial Interfaces:
Other peripherals:
Standard ARM test/debug interface for compatibility with existing tools.
Emulation trace module supports real-time trace.
Single 3.3 V power supply (3.0 V to 3.6 V).
Four reduced power modes: idle, sleep, power-down, and deep power-down.
Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0
and port 2 can be used as edge sensitive interrupt sources.
Processor wake-up from Power-down mode via any interrupt able to operate during
Power-down mode (includes external interrupts, RTC interrupt, USB activity, port 0/2
pin interrupt, Ethernet wake-up interrupt (LPC2460 only), CAN bus activity (LPC2460
only)).
2
S, and SD/MMC interface as well as for memory-to-memory transfers.
Ethernet MAC with MII/RMII interface and associated DMA controller (LPC2460
only). These functions reside on an independent AHB.
USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and
associated DMA controller.
Four UARTs with fractional baud rate generation, one with modem control I/O, one
with IrDA support, all with FIFO.
CAN controller with two channels (LPC2460 only).
SPI controller.
Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate
for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller.
Three I
I
the GPDMA.
SD/MMC memory card interface.
160 General purpose I/O pins with configurable pull-up/down resistors.
10-bit ADC with input multiplexing among 8 pins.
10-bit DAC.
Four general purpose timers/counters with 8 capture inputs and 10 compare
outputs. Each timer block has an external count input.
Two PWM/timer blocks with support for three-phase motor control. Each PWM has
an external count inputs.
RTC with separate power domain. Clock source can be the RTC oscillator or the
APB clock.
2 kB SRAM powered from the RTC power pin, allowing data to be stored when the
rest of the chip is powered off.
WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator,
the RTC oscillator, or the APB clock.
2
S (Inter-IC Sound) interface for digital audio input or output. It can be used with
2
C-bus interfaces (one with open-drain and two with standard port pins).
Rev. 05 — 24 February 2010
Flashless 16-bit/32-bit microcontroller
LPC2420/2460
© NXP B.V. 2010. All rights reserved.
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