LPC2420FET208,551 NXP Semiconductors, LPC2420FET208,551 Datasheet - Page 55

• Manufacturer Part Number: LPC2420FET208,551
• Description: IC ARM7 MCU 16BIT T208FBGA
• Manufacturer: NXP Semiconductors
• Series: LPC2400r

Specifications of LPC2420FET208,551

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 72MHz
• Connectivity: EBI/EMI, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Type: ROMless
• Ram Size: 82K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-TFBGA
• Processor Series: LPC2420
• Core: ARM7
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 98 KB
• Interface Type: SPI, I2C, I2S, USB, SSP
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 160
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Processor To Be Evaluated: ARM7TDMI-S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-5216

Table 10.
C
Symbol
Common to read and write cycles
t
Read cycle parameters
t
t
t
t
t
t
t
t
t
Write cycle parameters
t
t
t
t
t
t
t
CSLAV
OELAV
CSLOEL
am
h(D)
CSHOEH
OEHANV
OELOEH
BLSLAV
CSHBLSH
CSLWEL
CSLBLSL
WELDV
CSLDV
WELWEH
BLSLBLSH
WEHANV
L
= 30 pF, T
Parameter
CS LOW to address valid
time
OE LOW to address valid
time
CS LOW to OE LOW time
memory access time
data input hold time
CS HIGH to OE HIGH time
OE HIGH to address invalid
time
OE LOW to OE HIGH time
BLS LOW to address valid
time
CS HIGH to BLS HIGH time
CS LOW to WE LOW time
CS LOW to BLS LOW time
WE LOW to data valid time
CS LOW to data valid time
WE LOW to WE HIGH time
BLS LOW to BLS HIGH
time
WE HIGH to address invalid
time
Dynamic characteristics: Static external memory interface
amb
=
−
40
°
C to 85
[1][2]
[1][6]
°
C, V
[1]
DD(DCDC)(3V3)
Conditions
= V
DD(3V3)
[3][4]
[5]
[3]
[3]
[3]
= 3.0 V to 3.6 V, AHB clock = 1 MHz
Min
−0.29
−0.29
−0.78 + T
(WAITRD − WAITOEN + 1) ×
T
1.29
−0.49
−0.20
−0.59 + (WAITRD −
WAITOEN + 1) × T
−0.39
−0.88
−0.88 + T
WAITWEN)
−0.88
0.68
0
−0.78 + T
(WAITWR − WAITWEN + 1)
−0.88 + T
(WAITWR − WAITWEN + 3)
0 + T
cy(CCLK)
cy(CCLK)
− 8.11
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
× WAITOEN 0 + T
× (1 +
×
×
cy(CCLK)
Typ
0.20
0.20
(WAITRD − WAITOEN + 1) ×
T
4.22
0
0.20
0 + (WAITRD − WAITOEN +
1) × T
0
0.49
0.10 + T
WAITWEN)
0.49
2.54
2.64
0 + T
WAITWEN + 1)
0 + T
WAITWEN + 3)
0.20 + T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
− 9.57
× WAITOEN
× (WAITWR −
× (WAITWR −
× (1 +
Max
2.54
2.54
0.49 + T
(WAITRD − WAITOEN + 1) ×
T
5.20
0.20
2.44
0.10 + (WAITRD −
WAITOEN + 1) × T
2.54
0.68
0.20 + T
WAITWEN)
0.98
5.86
4.79
0.10 + T
(WAITWR − WAITWEN + 1)
0.59 + T
(WAITWR − WAITWEN + 3)
2.74 + T
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
cy(CCLK)
− 12.70
× WAITOEN
× (1 +
×
×
cy(CCLK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns