SC16C550BIA44 NXP Semiconductors, SC16C550BIA44 Datasheet - Page 13

• Manufacturer Part Number: SC16C550BIA44
• Description: UART, 16BYTE FIFO, 16C550, PLCC44
• Manufacturer: NXP Semiconductors

Specifications of SC16C550BIA44

• No. Of Channels: 1
• Data Rate: 3Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Uart Features: Automatic Hardware Flow Control, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes

NXP Semiconductors
SC16C550B_5
Product data sheet
Fig 9.
RTS
IOR
RX
(1) RTS is de-asserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the
(2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is more
(3) When the receive FIFO is full, the first receive buffer register read re-asserts RTS.
sixteenth byte.
than one byte of space available.
RTS functional timing waveforms, RX FIFO trigger level = 14 bytes
6.4 Hardware/software and time-out interrupts
byte 14
Following a reset, the transmitter interrupt is enabled, the SC16C550B will issue an
interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be
serviced prior to continuing operations. The ISR register provides the current singular
highest priority interrupt only. Only after servicing the higher pending interrupt will the
lower priority be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC16C550B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
center of each stop bit received or each time the Receive Holding Register (RHR) is read.
The actual time-out value is 4 character time, including data information length, start bit,
parity bit, and the size of stop bit, that is, 1 , 1.5 , or 2 bit times.
RTS released after the
first data bit of byte 16
byte 15
Rev. 05 — 1 October 2008
Start
byte 16
Stop
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Start
SC16C550B
byte 18
© NXP B.V. 2008. All rights reserved.
Stop
002aaa051
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