SC16C550BIA44 NXP Semiconductors, SC16C550BIA44 Datasheet - Page 23

• Manufacturer Part Number: SC16C550BIA44
• Description: UART, 16BYTE FIFO, 16C550, PLCC44
• Manufacturer: NXP Semiconductors

Specifications of SC16C550BIA44

• No. Of Channels: 1
• Data Rate: 3Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Uart Features: Automatic Hardware Flow Control, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes

NXP Semiconductors
SC16C550B_5
Product data sheet
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 15.
Bit
7
6
5
4
3
2
1:0
Symbol
LCR[7]
LCR[6]
LCR[5]
LCR[4]
LCR[3]
LCR[2]
LCR[1:0]
Line Control Register bits description
Description
Divisor latch enable. The internal baud rate counter latch and Enhance
Feature mode enable.
Set break. When enabled, the Break control bit causes a break condition to
be transmitted (the TX output is forced to a logic 0 state). This condition exists
until disabled by setting LCR[6] to a logic 0.
Set parity. If the parity bit is enabled, LCR[5] selects the forced parity format.
Programs the parity conditions (see
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1, LCR[4]
selects the even or odd parity format.
Parity enable. Parity or no parity can be selected via this bit.
Stop bits. The length of stop bit is specified by this bit in conjunction with the
programmed word length (see
Word length bits [1:0]. These two bits specify the word length to be
transmitted or received (see
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch and enhanced feature register enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 = parity is not forced (normal default condition)
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1 for
the transmit and receive data
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0 for
the transmit and receive data
logic 0 = odd parity is generated by forcing an odd number of logic 1s in the
transmitted data. The receiver must be programmed to check the same
format (normal default condition).
logic 1 = even parity is generated by forcing an even number of logic 1s in
the transmitted data. The receiver must be programmed to check the same
format.
logic 0 = no parity (normal default condition)
logic 1 = a parity bit is generated during the transmission, receiver checks
the data and parity for transmission errors
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Rev. 05 — 1 October 2008
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Table
Table
18).
Table
17).
16).
SC16C550B
© NXP B.V. 2008. All rights reserved.
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