SC16C550BIA44 NXP Semiconductors, SC16C550BIA44 Datasheet - Page 18

• Manufacturer Part Number: SC16C550BIA44
• Description: UART, 16BYTE FIFO, 16C550, PLCC44
• Manufacturer: NXP Semiconductors

Specifications of SC16C550BIA44

• No. Of Channels: 1
• Data Rate: 3Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Uart Features: Automatic Hardware Flow Control, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes

NXP Semiconductors
7. Register descriptions
Table 9.
[1]
[2]
[3]
[4]
[5]
SC16C550B_5
Product data sheet
A2 A1 A0
General Register Set
0
0
0
0
0
0
1
1
1
1
Special Register Set
0
0
The value shown represents the register’s initialized hexadecimal value; X = not applicable.
These registers are accessible only when LCR[7] is set to a logic 0.
These functions are not supported in the HVQFN32 package, and should not be written.
OUT2 pin is not supported in the HVQFN32 package.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
SC16C550B internal registers
Register
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
[5]
[2]
Table 9
The assigned bit functions are more fully defined in
Default
[1]
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
details the assigned bit functions for the twelve SC16C550B internal registers.
Bit 7
bit 7
bit 7
RX
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
reserved
FIFO
data
error
DCD
bit 7
bit 7
bit 15
Bit 6
bit 6
bit 6
RX
trigger
(LSB)
FIFOs
enabled
set break set parity even
transmit
empty
RI
bit 6
bit 6
bit 14
Rev. 05 — 1 October 2008
Bit 5
bit 5
bit 5
reserved reserved
0
auto flow
control
enable
transmit
holding
empty
DSR
bit 5
bit 5
bit 13
Bit 4
bit 4
bit 4
0
parity
loopback
break
interrupt
CTS
bit 4
bit 4
bit 12
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
OUT2
framing
error
bit 3
bit 3
bit 11
Section 7.1
DCD
[3]
[4]
Bit 2
bit 2
bit 2
receive
line status
interrupt
TX FIFO
reset
INT
priority
bit 1
stop bits
OUT1
parity
error
bit 2
bit 2
bit 10
RI
through
SC16C550B
[3]
© NXP B.V. 2008. All rights reserved.
Bit 1
bit 1
bit 1
transmit
holding
register
RX FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
Section
DSR
7.10.
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
CTS
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