SC16C750BIB64 NXP Semiconductors, SC16C750BIB64 Datasheet - Page 12

UART, 64BYTE FIFO, 16C750, LQFP64

SC16C750BIB64

Manufacturer Part Number
SC16C750BIB64
Description
UART, 64BYTE FIFO, 16C750, LQFP64
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C750BIB64

No. Of Channels
1
Data Rate
3Mbps
Supply Voltage Range
2.25V To 5.5V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
64
Svhc
No SVHC (18-Jun-2010)
Operating
RoHS Compliant
Uart Features
Automatic Hardware Flow Control, Software Selectable Baud Rate Generator
Rohs Compliant
Yes

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NXP Semiconductors
SC16C750B_5
Product data sheet
6.6 DMA operation
Table 5.
The SC16C750B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in the
DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY output
pins.
Table 6.
Table 7.
Using 1.8432 MHz crystal
Desired
baud rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
Non-DMA mode
1 = FIFO empty
0 = at least 1 byte in FIFO
Non-DMA mode
1 = at least 1 byte in FIFO
0 = FIFO empty
Table 6
Baud rates using 1.8432 MHz or 3.072 MHz crystal
Effect of DMA mode on state of RXRDY pin
Effect of DMA mode on state of TXRDY pin
and
Divisor for
16 clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
Table 7
Rev. 05 — 17 October 2008
show this.
Baud rate
error
0.026
0.058
0.69
2.86
DMA mode
0-to-1 transition when FIFO empties
1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
DMA mode
0-to-1 transition when FIFO becomes full
1-to-0 transition when FIFO becomes empty
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Using 3.072 MHz crystal
Desired
baud rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
Divisor for
16 clock
3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5
SC16C750B
© NXP B.V. 2008. All rights reserved.
Baud rate
error
0.026
0.034
0.312
0.628
1.23
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