SC16C750BIB64 NXP Semiconductors, SC16C750BIB64 Datasheet - Page 5

• Manufacturer Part Number: SC16C750BIB64
• Description: UART, 64BYTE FIFO, 16C750, LQFP64
• Manufacturer: NXP Semiconductors

Specifications of SC16C750BIB64

• No. Of Channels: 1
• Data Rate: 3Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Uart Features: Automatic Hardware Flow Control, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes

NXP Semiconductors
Table 2.
SC16C750B_5
Product data sheet
Symbol
A2, A1, A0 29, 30,
AS
BAUDOUT 17
CS0, CS1,
CS2
CS
Pin description
Pin
PLCC44 LQFP64
31
28
14, 15,
16
-
5.2 Pin description
17, 18, 20
15
64
59, 61, 62
-
Fig 4.
Pin configuration for LQFP64
HVQFN32
16, 17, 18 I
-
8
-
7
TXRDY
XTAL1
XTAL2
DDIS
GND
IOW
IOW
IOR
IOR
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
AS
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Type
I
O
I
I
Rev. 05 — 17 October 2008
Description
Register select. A0 to A2 are used during read and write
operations to select the UART register to read from or write to.
Refer to
Address strobe. When AS is active (LOW), A0, A1, and A2 and
CS0, CS1, and CS2 drive the internal select logic directly; when AS
is HIGH, the register select and chip select signals are held at the
logic levels they were in when the LOW-to-HIGH transition of AS
occurred.
Baud out. BAUDOUT is a 16 clock signal for the transmitter
section of the UART. The clock rate is established by the reference
oscillator frequency divided by a divisor specified in the baud rate
generator divisor latches. BAUDOUT may also be used for the
receiver section by tying this output to RCLK.
Chip select. When CS0 and CS1 are HIGH and CS2 is LOW, these
three inputs select the UART. When any of these inputs are inactive,
the UART remains inactive (refer to AS description).
Table 3
SC16C750BIB64
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
for register addresses and refer to AS description.
SC16C750B
002aaa590
© NXP B.V. 2008. All rights reserved.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D4
n.c.
D3
D2
n.c.
D1
D0
n.c.
V
n.c.
RI
n.c.
DCD
DSR
n.c.
CTS
CC
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