SC16C750BIB64 NXP Semiconductors, SC16C750BIB64 Datasheet - Page 29

• Manufacturer Part Number: SC16C750BIB64
• Description: UART, 64BYTE FIFO, 16C750, LQFP64
• Manufacturer: NXP Semiconductors

Specifications of SC16C750BIB64

• No. Of Channels: 1
• Data Rate: 3Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Uart Features: Automatic Hardware Flow Control, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes

NXP Semiconductors
Table 26.
T
[1]
[2]
[3]
[4]
SC16C750B_5
Product data sheet
Symbol
t
t
t
t
t
t
N
24d
25d
26d
27d
28d
RESET
amb
Fig 7.
Applies to external clock, crystal oscillator max 24 MHz.
Applicable only when AS is tied LOW.
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
Reset pulse must happen when these signals are inactive: CS, CS2, CS1, CS0, IOR, IOR, IOW, IOW.
= 40 C to +85 C; tolerance of V
General read timing when using AS signal
Parameter
delay from IOW to reset
interrupt
delay from stop to set RXRDY
delay from IOR to reset
RXRDY
delay from IOW to set TXRDY
delay from start to reset
TXRDY
Reset pulse width
baud rate divisor
CS1, CS0
Dynamic characteristics
IOR, IOR
D0 to D7
A0 to A2
DDIS
CS2
10.1 Timing diagrams
AS
t
8d
t
4w
t
5s
t
t
6s
7d
…continued
CC
t
11d
address
valid
t
=
12d
Conditions
active
t
10 %, unless otherwise specified.
valid
7w
t
active
t
5h
6h
Rev. 05 — 17 October 2008
data
t
12h
[3]
[3]
[4]
t
7h
t
11h
Min
100
V
t
1
-
-
-
-
-
9d
CC
= 2.5 V
1T
8T
2
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Max
16
100
100
100
RCLK
RCLK
-
1
Min
40
V
1
-
-
-
-
-
CC
= 3.3 V
1T
8T
2
Max
16
45
45
45
RCLK
RCLK
-
1
SC16C750B
Min
40
V
1
-
-
-
-
-
© NXP B.V. 2008. All rights reserved.
CC
002aaa331
= 5.0 V
1T
8T
2
Max
16
40
40
40
RCLK
RCLK
-
1
29 of 44
Unit
ns
s
ns
ns
s
ns