SC16C750BIB64 NXP Semiconductors, SC16C750BIB64 Datasheet - Page 7

• Manufacturer Part Number: SC16C750BIB64
• Description: UART, 64BYTE FIFO, 16C750, LQFP64
• Manufacturer: NXP Semiconductors

Specifications of SC16C750BIB64

• No. Of Channels: 1
• Data Rate: 3Mbps
• Supply Voltage Range: 2.25V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Svhc: No SVHC (18-Jun-2010)
• Operating: RoHS Compliant
• Uart Features: Automatic Hardware Flow Control, Software Selectable Baud Rate Generator
• Rohs Compliant: Yes

NXP Semiconductors
Table 2.
SC16C750B_5
Product data sheet
Symbol
RCLK
RESET
IOR
IOR
RI
RTS
RXRDY
RX
TX
Pin description
Pin
PLCC44 LQFP64
10
39
25
24
43
36
32
11
13
54
32
10
9
38
26
21
55
58
…continued
HVQFN32
4
24
-
14
-
21
19
5
6
Type
I
I
I
I
I
O
O
I
O
Rev. 05 — 17 October 2008
Description
Receiver clock. RCLK is the 16 baud rate clock for the receiver
section of the UART.
Master Reset. When active (HIGH), RESET clears most UART
registers and sets the levels of various output signals.
Read inputs. When either IOR or IOR is active (LOW or HIGH,
respectively) while the UART is selected, the CPU is allowed to
read status information or data from a selected UART register. Only
one of these inputs is required for the transfer of data during a read
operation; the other input should be tied to its inactive level (that is,
IOR tied LOW or IOR tied HIGH).
Ring indicator. RI is a modem status signal. Its condition can be
checked by reading bit 6 (RI) of the Modem Status Register. Bit 2
( RI) of the MSR indicates that RI has changed from a LOW to a
HIGH level since the last read from the MSR. If the modem status
interrupt is enabled when this transition occurs, an interrupt is
generated.
Request to send. When active, RTS informs the modem or data
set that the UART is ready to receive data. RTS is set to the active
level by setting the RTS Modem Control Register bit and is set to
the inactive (HIGH) level either as a result of a Master Reset or
during Loopback mode operations or by clearing bit 1 (RTS) of the
MCR. In the auto-RTS mode, RTS is set to the inactive level by the
receiver threshold control logic.
Receiver ready. Receiver Direct Memory Access (DMA) signaling
is available with RXRDY. When operating in the FIFO mode, one of
two types of DMA signaling can be selected using the FIFO Control
Register bit 3 (FCR[3]). When operating in the 16C450 mode, only
DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in
which a transfer is made between CPU bus cycles. Mode 1
supports multi-transfer DMA in which multiple transfers are made
continuously until the receiver FIFO has been emptied. In DMA
mode 0 (FCR[0] = 0 or FCR[0] = 1, FCR[3] = 0), when there is at
least one character in the receiver FIFO or receiver holding register,
RXRDY is active (LOW). When RXRDY has been active but there
are no characters in the FIFO or holding register, RXRDY goes
inactive (HIGH). In DMA mode 1 (FCR[0] = 1, FCR[3] = 1), when
the trigger level or the time-out has been reached, RXRDY goes
active (LOW); when it has been active but there are no more
characters in the FIFO or holding register, it goes inactive (HIGH).
Serial data input. RX is serial data input from a connected
communications device.
Serial data output. TX is composite serial data output to a
connected communication device. TX is set to the marking (HIGH)
level as a result of Master Reset.
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
SC16C750B
© NXP B.V. 2008. All rights reserved.
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