AD9957/PCBZ Analog Devices Inc, AD9957/PCBZ Datasheet - Page 17

D/A Converter Evaluation Board

AD9957/PCBZ

Manufacturer Part Number
AD9957/PCBZ
Description
D/A Converter Evaluation Board
Manufacturer
Analog Devices Inc
Series
AgileRF™r
Datasheet

Specifications of AD9957/PCBZ

Silicon Manufacturer
Analog Devices
Application Sub Type
Direct Digital Synthesizer
Kit Application Type
Clock & Timing
Silicon Core Number
AD9957
Kit Contents
Board
Main Purpose
Timing: DDS Modulators
Embedded
No
Utilized Ic / Part
AD9957
Primary Attributes
14-Bit DAC, 32-Bit Tuning Word Width
Secondary Attributes
1GHz, Graphical User Interface
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9957/PCBZ
Manufacturer:
LT
Quantity:
962
QUADRATURE MODULATION MODE
A block diagram of the AD9957 operating in QDUC mode is
shown in Figure 26; grayed items are inactive. The parallel input
accepts 18-bit I- and Q-words in time-interleaved fashion. That
is, an 18-bit I-word is followed by an 18-bit Q-word, then the
next 18-bit I-word, and so on. One 18-bit I-word and one 18-bit
Q-word together comprise one internal sample. The data assem-
bler and formatter de-interleave the I- and Q-words so that each
sample propagates along the internal data pathway in parallel
fashion. Both I and Q data paths are active; the parallel data
clock (PDCLK) serves to synchronize the input of I/Q data to
the AD9957.
TxENABLE
PDCLK
I/Q IN
FTW
18
PW
TIMING AND CONTROL
PROGRAMMING
PARALLEL DATA
REGISTERS
3
18
16
16
18
QS
Q
IS
I
SERIAL I/O
PORT
INTERNAL CLOCK TIMING AND CONTROL
Figure 26. Quadrature Modulation Mode
I Q
RAM
IS QS
Rev. B | Page 17 of 64
OSK
AD9957
cos (ωt+θ)
θ
ω
sin (ωt+θ)
CLOCK
CONTROL
DDS
POWER
DOWN
The PROFILE and I/O_UPDATE pins are also synchronous to
the PDCLK.
The DDS core provides a quadrature (sine and cosine) local
oscillator signal to the quadrature modulator, where the
interpolated I and Q samples are multiplied by the respective
phase of the carrier and summed together, producing a
quadrature modulated data stream. This data stream is routed
through the inverse sinc filter (optionally), and the output
scaling multiplier. Then it is applied to the 14-bit DAC to
produce the quadrature modulated analog output signal.
2
2
SYSCLK
DAC GAIN
PLL
÷2
8
OUTPUT
FACTOR
SCALE
8-BIT
AUX
DAC
14-BIT
DAC
DAC_RSET
IOUT
IOUT
REFCLK_OUT
REF_CLK
REF_CLK
XTAL_SEL
AD9957

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