AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 16

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9553
THEORY OF OPERATION
OVERVIEW
The AD9553 can receive up to two input reference clocks, REFA
and REFB. Both input clock paths include an optional divide-by-5
(÷5) prescaler, an optional ×2 frequency multiplier, and a 14-bit
programmable divider. Alternatively, the user can program the
device to operate with one differential input clock (instead of
two single-ended input clocks) via the serial I/O port. In the
differential operating mode, the REFB path is inactive.
The AD9553 also has a dedicated XTAL input for direct connec-
tion of an optional 25 MHz crystal resonator. This allows for a
backup clock signal useful for holdover operation in case both
input references fail. The XTAL clock path includes a fixed ×2
frequency multiplier and a 14-bit programmable divider.
The AD9553 includes a switchover control block that auto-
matically handles switching from REFA to REFB (or vice versa)
in the event of a reference failure. If both REFA and REFB fail,
however, then the switchover control block automatically enters
holdover mode by selecting the XTAL clock signal (assuming
the presence of a crystal resonator at the XTAL input).
Generally, the clock signals that appear at the input to the clock
multiplexer (see Figure 27) all operate at the same frequency.
Thus, the frequency at the input to the PLL (FPFD in Figure 27)
is the same regardless of the signal selected by the clock multi-
plexer. The PLL converts FPFD to a frequency within the operating
range of the VCO (3.35 GHz to 4.05 GHz) based on the value of
the feedback divider (N). The VCO prescaler (P
VCO output frequency by an integer factor of 5 to 11, resulting in
an intermediate frequency in the range of 305 MHz to 810 MHz.
REFB/REFA
SEL REFB
REFA
XTAL
XTAL
DCXO
CTRL
REF
SEL
CONTROL
TUNING
DIFF
REF
SWITCHOVER
REFERENCE
0
1
CONTROL
DET
A
DET
B
÷5
÷5
DET
XO
XO
÷5
÷5
0
1
0
1
A
B
CLOCK MUX
HOLD
×2
×2
×2
DET XO
DET A
DET B
×2
×2
1
0
1
0
A
B
0
) reduces the
14
14
÷R
14
DET
÷R
÷R
R
DET
DET
R
R
XO
XO
A
B
A
B
FDBK/2
FPFD/2
Figure 27. Detailed Block Diagram
UP/2
XO
CLOCK
MUX
Rev. A | Page 16 of 44
TEST
R
XO
FPFD
, DCXO CTRL
LOCKED
R
R
N, P
A
B
DETECT
1
, ×2
, ×2
REF DIFF
LOCK
REF SEL
0
0
FDBK
P
F
D
, P
A
B
TEST
, ÷5
, ÷5
1
DN
UP
HOLD
, P
The 10-bit P
frequency to yield the final output clock frequencies at OUT1
and OUT2, respectively.
Thus, the frequency translation ratio from the reference input
to the output depends on the selection of the ÷5 prescalers; the
×2 frequency multipliers; the values of the three R dividers; the
N divider; and the P
set automatically via the preconfigured divider settings per the Ax
and Yx pins (see the Preset Frequencies section). Alternatively, the
user can custom program these parameters via the serial I/O port
(see the Serial Control Port and Register Map sections), which allows
the device to accommodate custom frequency translation ratios.
PRESET FREQUENCIES
The frequency selection pins (A3 to A0 and Y5 to Y0) allow the
user to hardwire the device for preset input and output frequencies
based on the pin logic states (see Figure 27). The pins decode
ground or open connections as Logic 0 or Logic 1, respectively.
To have access to the device control registers via the SPI port, the
user must select Pin Y5 to Pin Y0 = 000000 and/or Pin A3 to
Pin A0 = 0000. Doing so causes Pin 12 through Pin 14 to function
as SPI port control pins instead of output mode control pins (see
the Output Driver Mode Control section). Note that after selecting
SPI mode, the user must write a Logic 1 to Bit 0 of Register 0x32
and Register 0x34 to enable the registers as the source of the OUT1
and OUT2 mode control bits (see Figure 31 and the Output Driver
Mode Control section).
A
B
2
20
CHARGE
PLL
÷N
PUMP
N
1
0
FILTER
FILTER
LOOP
1
and P
3350MHz
4050MHz
SPI CTRL
VCO
TO
DIVIDER SETTINGS
PRECONFIGURED
REGISTER BANK
2
0
dividers can further reduce the P
, P
5 TO 11
1
3
, and P
P
P
0
0
AD9553
10
10
2
P
P
P
P
dividers. These parameters are
2
2
1
1
CONTROL
OUTPUT
MODE
1 0
3
3
4
6
3
2
2
3
OUT2
OUT1
OUTPUT MODE/
SERIAL PORT
A[3:0]
Y[5:0]
0
output