AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 23

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Loop Filter
The charge pump in the PFD delivers current to the loop filter
(see Figure 30). The components primarily responsible for the
bandwidth of the loop filter are external and connect between
Pin 16 and Pin 17.
The internal portion of the loop filter has two configurations: one
is for low loop bandwidth applications (~170 Hz) and the other is
for medium (~20 kHz)/high (~75 kHz) bandwidth applications.
The low loop bandwidth condition applies when the feedback
divider value (N) is 214 (16,384) or greater. Otherwise, the
medium/high loop bandwidth configuration is in effect. The
feedback divider value depends on the configuration of the Ax
and Yx pins per Table 16.
The bandwidth of the loop filter primarily depends on three
external components (R, C1, and C2). There are two sets of recom-
mended values for these components corresponding to the low and
medium/high loop bandwidth configurations (see Table 17).
Table 17. External Loop Filter Components
A3 to A0 Pins
0001 to 1100, and 1111
1110
1101 and 1110
1
2
To achieve the best jitter performance in applications requiring a
loop bandwidth of less than 1 kHz, C1 and C2 must have an
insulation resistance of at least 500 ΩF.
PLL Locked Indicator
The PLL provides a status indicator that appears at Pin 20
(LOCKED). When the PLL acquires phase lock, the LOCKED
pin switches to a Logic 1 state. When the PLL loses lock,
however, the LOCKED pin returns to a Logic 0 state.
CHARGE
The 20 kHz loop bandwidth case only applies when the A3 pin to A0 pin =
The 75 kHz loop bandwidth case only applies when the A3 pin to A0 pin =
1110 and the Y5 pin to Y0 pin = 111111.
1101 and the Y5 pin to Y0 pin = 101101 through 110010, or when the A3 pin
to A0 pin = 1110 and the Y5 pin to Y0 pin = 110011.
FROM
PUMP
16
1
FILTER
375Ω
C1
R
2
BUFFER
Figure 30. External Loop Filter
C2
STATE FOR N ≥ 16384
SWITCHES CHANGE
17
400kΩ
R
6.8 kΩ
12 kΩ
12 kΩ
LDO
AD9553
C1
47 nF
51 pF
51 pF
CONTROL
LOGIC
3kΩ
170pF
C2
1 µF
220 nF
220 nF
Loop
Bandwidth
0.17 kHz
20 kHz
75 kHz
53pF
TO
VCO
Rev. A | Page 23 of 44
Alternatively, the LOCKED pin serves as a test port allowing the
user to monitor one-of-four internal clocks. Register 0x17[3:1]
controls the test port as shown in Table 18.
Table 18. LOCKED Pin Output Control
Register 0x17[3:1]
0XX
100
101
110
111
Output Dividers
The output divider section consists of three dividers: P
The P
frequency and reduces it by a factor of 5 to 11 (selectable). This
brings the frequency down to a range between 305 MHz and
810 MHz.
The output of the P
and the P
OUT1 and the P
The P
1 to 1023, which results in a frequency at OUT1 or OUT2 that
is an integer submultiple of the frequency at the output of the P
divider.
Output Driver Configuration
The user has complete control over all configurable parameters
of the OUT1 and OUT2 drivers via the OUT1 and OUT2 driver
control registers (Register 0x32 and Register 0x34, respectively,
as shown in Figure 31). To alter the parameters from their default
values, the user must use the SPI port to program the driver
control registers as desired.
The OUT1 and OUT2 drivers are configurable in terms of the
following parameters:
•
•
•
•
•
Output Driver Mode Control
Three mode control bits establish the logic family and pin function
of the output drivers. The three bits originate either from Bits[5:3]
of Register 0x32 and Register 0x34 or from the decode logic
associated with the OM2 to OM0 pins as shown in Figure 31.
Note that Bit 0 of Register 0x32 and Register 0x34 determines
the source of the three mode control bits for the associated
output driver. Specifically, when Bit 0 of the register is Logic 0
(default), the source of the mode control bits for the associated
driver is the OM2 to OM0 pin decoder. When Bit 0 is Logic 1, the
source of the mode control bits is from Bits[5:3] of Register 0x32
and Register 0x34.
Logic family (via mode control)
Pin function (via mode control but only applies to the
CMOS family)
Polarity (only applies to the CMOS family)
Drive current
Power-down
0
1
divider (or VCO frequency prescaler) accepts the VCO
and P
2
divider. The P
2
dividers are each programmable over a range of
2
divider establishes the frequency at OUT2.
0
divider independently drives the P
LOCKED Pin Output
PLL locked indication (default)
Crystal oscillator clock signal
PFD pump-up clock divided-by-2
PFD reference input clock divided-by-2
PLL feedback to PFD clock divided-by-2
1
divider establishes the frequency at
0
AD9553
, P
1
divider
1
, and P
2
.
0