AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 37

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLL and Output Frequency Control (Register 0x11 to Register 0x19)
Table 31.
Address
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
Bit
[7:0]
[7:0]
[7:0]
[7:4]
3
2
1
0
[7:0]
[7:6]
[5:0]
[7:4]
3
[2:1]
0
[7:5]
[4:0]
[7:0]
Bit Name
Unused
Feedback divider (N)
Feedback divider (N)
Feedback divider (N)
Enable SPI control of
feedback divider
Enable SPI control of
output dividers
Unused
Reset PLL
P
P
P
P
Enable test port
Test mux
Unused
P
Unused
Unused
1
1
2
2
0
divider
divider
divider
divider
divider
Description
Unused.
Bits[19:12] of the 20-bit feedback divider (N).
Bits[11:4] of the 20-bit feedback divider (N).
Bits[3:0] of the 20-bit feedback divider (N). Default is N = 0x80000 (524,288). The feedback
divider bits are ineffective unless Register 0x14[3] = 1.
Enables SPI port control of the feedback divider value (N).
0 = the A3 to A0 and Y5 to Y0 pins define N per Table 16 (default).
1 = the 20-bit value in the feedback divider register defines N.
Enables SPI port control of the output dividers P
0 = the Y5 to Y0 pins define the output divider values per Table 15 (default).
1 = the SPI port registers (0x15, 0x16, 0x18) define the output divider values.
Unused.
Controls initialization of the PLL.
0 = normal operation (default).
1 = resets the counters and logic associated with the PLL but does not affect the output dividers.
Bits[9:2] of the 11-bit P
Bits[1:0] of the 11-bit P
divider bits are ineffective unless Register 0x14[2] = 1.
Bits[9:4] of the 11-bit P
Bits[3:0] of the 11-bit P
Enables use of the LOCKED pin as a test port.
0 = the LOCKED pin indicates PLL status (default).
1 = the LOCKED pin outputs a test signal per Register 0x17[2:1].
Test mux select bits.
00 = crystal oscillator output (XO).
01 = PFD pump up clock divided-by-2 (UP/2).
10 = PFD reference input clock divided-by-2 (FPFD/2).
11 = PFD feedback clock divided-by-2 (FDBK/2).
Unused.
Bits[2:0] of the P
000 = invalid.
001 = divide-by-5.
010 = divide-by-6.
011 = divide-by-7.
100 = divide-by-8.
101 = divide-by-9.
110 = divide-by-10.
111 = divide-by-11.
Unused.
Unused.
Rev. A | Page 37 of 44
0
divider. The P
1
1
2
2
divider.
divider (the default P
divider.
divider. The P
0
divider bits are ineffective unless Register 0x14[2] = 1.
2
divider bits are ineffective unless Register 0x14[2] = 1.
1
divider register value is 128 decimal). The P
0
, P
1
, and P
2
.
AD9553
1