AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 22

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9553
The user can override the automatic switchover functions
(revertive and nonrevertive) and manually select the REFA
or REFB signal by programming Register 0x29[7:6] = 10 or 11,
respectively. Note, however, that the desired signal (REFA or
REFB) must be present for the device to select it.
The user can also force the device to switch to REFB by applying
a Logic 1 to the external SEL REFB pin. This overrides a REFA
selection invoked by either the revertive/nonrevertive logic or
when Register 0x29[7:6] = 10. Note, however, that REFB must
be present to be selected by the device.
PLL (PFD, Charge Pump, VCO, Feedback Divider)
The PLL (see Figure 27) consists of a phase/frequency detector
(PFD), a partially integrated analog loop filter (see Figure 30),
an integrated voltage controlled oscillator (VCO), and a 20-bit
programmable feedback divider. The PLL generates a 3.35 GHz
to 4.05 GHz clock signal that is phase locked to the active input
reference signal, and its frequency is the phase detector frequency
(FPFD) multiplied by the feedback divider value (N).
The PFD of the PLL drives a charge pump that increases, decreases,
or holds constant the charge stored on the loop filter capacitors
(both internal and external). The stored charge results in a voltage
that sets the output frequency of the VCO. The feedback loop of
the PLL causes the VCO control voltage to vary in such a way as
to phase lock the PFD input signals. Note that the PFD supports
input frequencies spanning 13.3 kHz to 100 MHz (implying that
input frequencies between 8 kHz and 13.3 kHz must use the ×2
frequency multiplier in the input path).
FROM REFA
FROM REFB
FROM XTAL
NON-REVERTIVE
SELECT REFA
SELECT REFB
INPUT
INPUT
INPUT
REVERTIVE
R
R
R
FDBK
XO
A
B
REG 0x29[7:6]
DIVIDER
DIVIDER
DIVIDER
÷
÷
÷
00
01
10
11
DETECTOR
SIGNAL
SPI SELECT REFA/B
NON-REVERTIVE
REVERTIVE/
LOGIC
LOGIC
Figure 29. Switchover/Holdover Block Diagram
XTAL PRESENT
REFB PRESENT
REFA PRESENT
SEL B/A
SEL B/A
Rev. A | Page 22 of 44
SEL B/A
The PLL has a VCO with 128 frequency bands spanning a range
of 3350 MHz to 4050 MHz (3700 MHz nominal). However, the
actual operating frequency within a particular band depends on
the control voltage that appears on the loop filter capacitor. The
control voltage causes the VCO output frequency to vary linearly
within the selected band. This frequency variability allows the
control loop of the PLL to synchronize the VCO output signal
with the reference signal applied to the PFD.
Typically, selection of the VCO frequency band (as well as gain
adjustment) occurs automatically as part of the automatic VCO
calibration process of the device, which initiates at power up (or
reset). Alternatively, the user can force VCO calibration by first
enabling SPI control of VCO calibration (Register 0x0E[2] = 1)
and then writing a 1 to the calibrate VCO bit (Register 0x0E[7]).
Note that VCO calibration centers the dc operating point of the
VCO control signal. Furthermore, during VCO calibration, the
output drivers provide a static dc signal.
To facilitate system debugging, the user can override the VCO band
setting by first enabling SPI control of VCO band (Register 0x0E[0]
= 1) and then writing the desired value to Register 0x10[7:1].
The feedback divider (N-divider) sets the frequency multi-
plication factor of the PLL in integer steps over a 20-bit range.
Note that the N-divider has a lower limit of 32.
11
SEL B/A
SEL
REFB
SELECTION LOGIC
REFA/B
CONTROL
LOGIC
MUX
CLOCK
MUX
TO
PLL