AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 21

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

of a fixed component of 8 pF and a variable (programmable)
component of 0 pF to 15.75 pF.
After applying power to the AD9553 (or after a device reset),
the programmable component defaults to 2 pF. This establishes
the default load capacitance of 10 pF (8 pF fixed plus 2 pF
programmable).
To accommodate crystals with a specified load capacitance other
than 10 pF (8 pF to 23.75 pF), the user can adjust the program-
mable capacitance in 0.25 pF increments via Register 0x1B[5:0].
Note that when the user sets Register 0x1B[7] to 0 (enabling SPI
control of the XTAL tuning capacitors), the variable capacitance
changes from 2 pF (its default power-up value) to 15.75 pF due
to the default value of Register 0x1B[5:0]. This causes the crystal
load capacitance to be 23.75 pF until the user overwrites the
default contents of Register 0x1B[5:0].
A noncomprehensive, alphabetical list of crystal manufacturers
includes the following:
•
•
•
•
•
•
Although these crystals meet the load capacitance and motional
resistance requirements of the AD9553 according to their data
sheets, Analog Devices, Inc., does not guarantee their operation
with the AD9553, nor does Analog Devices endorse one supplier
of crystals over another.
Input Frequency Prescalers (Divide-by-5
The divide-by-5 prescalers provide the option to reduce the input
reference frequency by a factor of five. Note that the prescalers
physically precede the ×2 frequency multipliers. This allows the
prescalers to bring a high frequency reference clock down to a
frequency that is within the range of the ×2 frequency multipliers.
Input ×2 Frequency Multipliers (×2
The ×2 frequency multipliers provide the option to double the
frequency at their input; thereby taking advantage of a higher
frequency at the input to the PLL (FPFD). This provides greater
separation between the frequency generated by the PLL and the
modulation spur associated with the frequency at the PLL input.
However, increased reference spur separation comes at the expense
of the harmonic spurs introduced by the frequency multiplier.
As such, beneficial use of the frequency multiplier is application
specific. Note that the maximum input frequency to the ×2 fre-
quency multipliers must not exceed 125 MHz.
AVX/Kyocera
ECS
Epson Toyocom
Fox Electronics
NDK
Siward
A
, ×2
B
)
A
, Divide-by-5
Rev. A | Page 21 of 44
B
)
Input Clock Detectors
The three clock input sections (REFA, REFB, and XTAL) include
a dedicated monitor circuit that detects signal presence at the
input. The detectors provide input to the switchover control
block to support automatic reference switching and holdover
operation.
Switchover/Holdover
The AD9553 supports automatic reference switching and hold-
over functions. It also supports manual reference switching via
an external pin (SEL REFB) or via program control using the serial
I/O port. A block diagram of the switchover/holdover capability
appears in Figure 29. Note that the mux selects one of the three
input signals (REFA, REFB, or XTAL) routing it to the input of
the PLL. The selection of an input signal depends on which signals
are present along with the contents of Register 0x29[7:6] and
the logic level at the SEL REFB pin.
Note that each input signal has a dedicated signal presence detector.
Each detector uses the feedback signal from the PLL as a sampling
clock (which is always present due to the free-running VCO).
This allows the detectors to determine the presence or absence
of the input signals reliably. Note that the mux control logic uses
the detector signals directly in order to determine the need for a
switch to holdover operation.
Holdover occurs whenever the mux control logic determines
that both the REFA and REFB signals are not present, in which
case the device selects the XTAL signal if it is present. The excep-
tion is when Register 0x29[7:6] = 10 or 11, which disables the
holdover function. If none of the three input signals is present,
the device waits until at least one signal becomes present and
selects according to the device settings (Register 0x29[7:6] and
the logic level at the SEL REFB pin).
When the device is reset (or following a power-up), the internal
logic defaults to revertive switchover mode (Register 0x29[7:6] =
00). In revertive switchover mode, the device selects the REFA
signal whenever it is present. If REFA is not present, then the
device selects the REFB signal, if present, but returns to REFA
whenever it becomes available. That is, in revertive switchover
mode, the device favors REFA. If both REFA and REFB are not
present, the device switches to holdover mode.
When programmed for nonrevertive switchover mode
(Register 0x29[7:6] = 01), the device selects the REFA signal
if it is present. If REFA is not present, then the device selects
the REFB signal (if present). Even if REFA becomes available,
the device continues to use REFB until REFB fails. That is, in
nonrevertive switchover mode, the switch to REFB is permanent
unless REFB fails (or unless both REFA and REFB fail, in which
case the device switches to holdover mode).
AD9553