AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 17

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The Ax pins allow the user to select one of fifteen input reference
frequencies as shown in Table 14. The device sets the appropriate
divide-by-5 (÷5
divider (R
to the Ax pins.
The same settings apply to both the REFA and REFB input
paths. Furthermore, the ÷5, ×2, and R values cause the PLL
input frequency to be either 16 kHz or 40/3 kHz. There are two
exceptions. The first is for Pin A3 to Pin A0 = 1101, which
yields a PLL input frequency of 155.52/59 MHz. The second is for
Pin A3 to Pin A0 = 1110, which yields a PLL input frequency of
either 1.5625 MHz or 4.86 MHz depending on the Yx pins.
Table 14. Pin Configured Input Frequency, Ax Pins
Pin A3 to Pin A0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
2
3
4
For divide-by-5 and ×2 frequency scalers, “On” indicates active.
Using A0 to A3 = 0110 to yield a 25 MHz to 125 MHz conversion provides a loop bandwidth of 170 Hz. An alternate 25 MHz to 125 MHz conversion uses A0 to A3 = 1110, which
provides a loop bandwidth of 20 kHz.
Pin A3 to Pin A0 = 1101 only works with Pin Y5 to Pin Y0 =101101 through 110010.
Pin A3 to Pin A0 = 1110 only works with Pin Y5 to Pin Y0 =110011 or 111111.
2
3
4
A
, R
B
, R
A
, ÷5
XO
) values based on the logic levels applied
B
), multiply-by-2 (×2
f
0.008
1.536
2.048
16.384
19.44
25
38.88
61.44
77.76
122.88
125
1.544
155.52
25 or 77.76
200/3
REFA
, f
REFB
(MHz)
A
, ×2
B
), and input
Divide-by-5
Divide-by-5
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
On
Bypassed
Bypassed
Bypassed
Bypassed
1
Rev. A | Page 17 of 44
A
B
,
Note that the XTAL input is not available for holdover func-
tionality in the A3 to A0 = 1101 and 1110 pin configurations,
thus the undefined R
The Yx pins allow the user to select one of 52 output frequency
combinations (f
appropriate P
to the Yx pins. Note, however, that selections 101101 through
110010 require Pin A3 to Pin A0 = 1101, and selection 110011
requires Pin A3 to Pin A0 = 1110.
The value (N) of the PLL feedback divider and the control
setting for the charge pump current (CP) depend on a combi-
nation of both the Ax and Yx pin settings as shown in Table 16.
×2
On
Bypassed
Bypassed
Bypassed
Bypassed
On
Bypassed
Bypassed
Bypassed
Bypassed
On
On
Bypassed
Bypassed
Bypassed
SPI mode
A
, ×2
B
0
, P
OUT1
1
, and P
R
1
96
128
1024
1215
3125
2430
3840
4860
7680
3125
193
59
16
5000
A
and f
, R
XO
B
value.
2
(Decimal)
OUT2
settings based on the logic levels applied
) per Table 15. The device sets the
R
3125
3125
3125
3125
3125
3125
3125
3125
3125
3125
3125
3125
Undefined
Undefined
3750
XO
(Decimal)
AD9553