AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 26

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9553
JITTER TOLERANCE
Jitter tolerance is the ability of the AD9553 to maintain lock in
the presence of sinusoidal jitter. The AD9553 meets the input
jitter tolerance mask per Telcordia GR-253-CORE (see Figure 32).
The acceptable jitter tolerance is the region above the mask. The
trace showing the performance of the AD9553 in Figure 32
represents the limitations of the test equipment because the
AD9553 did not indicate loss of lock, even with the test
equipment injecting its maximum jitter level.
OUTPUT/INPUT FREQUENCY RELATIONSHIP
The frequency at OUT1 and OUT2 depends on the frequency at
the input to the PLL, the PLL feedback divider value (N), and the
output divider values (P
the frequency at OUT1 and OUT2 (f
are as follows:
where:
FPFD is the frequency at the reference input of the PFD.
N is the feedback divider value.
P
P
P
The operating frequency range of the PFD places a limitation
on FPFD as follows:
Note that for applications using the frequency selection pins in
conjunction with the XTAL input for the holdover function, the
maximum value of FPFD is 50 MHz (twice the 25 MHz default
crystal frequency).
0
1
2
is the VCO prescaler divider value.
is the OUT1 divider value.
is the OUT2 divider value.
13.3 kHz ≤ FPFD ≤ 100 MHz
f
f
100
OUT
0.1
OUT
1k
10
1
0.01
1
2
=
=
FPFD
FPFD
0.1








P
P
Figure 32. Jitter Tolerance
0
0
N
JITTER FREQUENCY (kHz)
N
×
×
0
, P
1
P
P
1
2
1
, and P








10
MASK
2
). The equations that define
OUT1
100
and f
AD9553
OUT2
1k
, respectively)
10k
Rev. A | Page 26 of 44
FPFD depends on the input frequency to the AD9553, the
configuration of the multiplexers for the ÷5 prescaler and ×2
frequency multiplier, and the value of the R
R
where:
f
K is the scale factor per Table 22.
FPFD is the frequency at the input to the phase frequency
detector.
Table 22. K as a Function of Input Multiplexer Configuration
Input
REFA
REFB
XTAL
1
This leads to the complete frequency translation formula
Specific numeric constraints apply as follows. Note that the
symbol
the series from the list within the curly brackets.
Additional constraints apply. One constraint is related to the
VCO and the other to the ×2 frequency multipliers in the REFA
and REFB paths. The VCO constraint is a consequence of its
limited bandwidth. However, the ×2 frequency multiplier
constraint only applies when the ÷5 prescalers are bypassed, but
it also requires that R
FPFD constraint. The additional constraints are as follows:
X
N/A means not applicable.
B
is equal to f
, or R
K
K
N ∈ {32, 33, …, 1,048,576}
P
P
P
3350 MHz ≤ f
3350 MHz ≤ f
f
FPFD
REFA/REFB
f
f
0
1
2
X
OUT
OUT
∈
∈ {5, 6, …, 11}
∈ {1, 2, …, 63}
∈ {1, 2, …, 63}
∈ {1, 2, …, 16,384}
XO
∈



) as follows:
1
2
1
5
indicates that the constraint is an element of one in
=
=
=
,
2
5
≤ 125 MHz (×2 multiplier with ÷5 bypassed)
REFA
f
f
f
1 ,
X
X
X




2 ,




×
÷5
Bypassed
Active
Bypassed
Active
Bypassed
Active
Bypassed
Active
N/A
, f
R
R
K



R
K
OUT1
REFB
OUT2
K
X
X
X
1




A




, or f








and R
× P
× P
P
P
0
0
N
0
×
N
0
XTAL
×
× P
× P
P
P
B
1
2
are large enough to satisfy the
.




1
2




≤ 4050 MHz
≤ 4050 MHz
×2
Bypassed
Bypassed
Active
Active
Bypassed
Bypassed
Active
Active
N/A
1
X
divider (either R
K
1
1/5
2
2/5
1
1/5
2
2/5
2
A
,