AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 31

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

By default, a read request reads the register value that is currently
in use by the AD9553. However, setting Register 0x04[0] = 1
causes the buffered registers to be read instead. The buffered
registers are the ones that take effect during the next I/O update.
INSTRUCTION WORD (16 BITS)
The MSB of the instruction word (see Table 25) is R/
indicates whether the instruction is a read or a write. The next
two bits, W1 and W0, are the transfer length in bytes. The final
13 bits are the address bits (Address Bits[A12:A0]) at which the
read or write operation is to begin.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0], which is interpreted
according to Table 24.
Address Bits[A12:A0] select the address within the register map
that is written to or read from during the data transfer portion
of the communication cycle. The AD9553 uses all of the 13-bit
address space. For multibyte transfers, this address is the starting
byte address.
Table 25. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/W
Table 26. Definition of Terms Used in Serial Control Port Timing Diagrams
Parameter
t
t
t
t
t
t
t
t
CLK
DV
DS
DH
S
H
HIGH
LOW
Figure 35. Relationship Between the Serial Control Port Register Buffers
OM1/SCLK
OM0/SDIO
OM2/CS
I14
W1
13
14
12
CONTROL
SERIAL
PORT
I13
W0
Description
Period of SCLK
Read data valid time (time from falling edge of SCLK to valid data on SDIO)
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Setup time between CS and SCLK
Hold time between CS and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
and the Control Registers
I12
A12
INPUT/OUTPUT
EXECUTE AN
REGISTER
UPDATE
UPDATE
I11
A11
AD9553
I10
A10
CORE
W
, which
I9
A9
Rev. A | Page 31 of 44
I8
A8
MSB/LSB FIRST TRANSFERS
The AD9553 instruction word and byte data can be MSB first or
LSB first. The default for the AD9553 is MSB first. The LSB first
mode can be set by writing a 1 to Register 0x00[6] and requires
that an I/O update be executed. Immediately after the LSB first
bit is set, all serial control port operations are changed to LSB
first order.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from high address to low address.
In MSB first mode, the serial control port internal address gen-
erator decrements for each data byte of the multibyte transfer cycle.
When LSB first = 1 (LSB first), the instruction and data bytes
must be written from LSB to MSB. Multibyte data transfers
in LSB first format start with an instruction byte that includes
the register address of the least significant data byte followed
by multiple data bytes. The serial control port internal byte
address generator increments for each data byte of the multibyte
transfer cycle.
The AD9553 serial control port register address decrements from
the register address just written toward 0x00 for multibyte I/O
operations if the MSB first mode is active (default). If the LSB
first mode is active, the serial control port register address
increments from the address just written toward 0x34 for
multibyte I/O operations.
Unused addresses are not skipped during multibyte I/O operations.
The user should write the default value to a reserved register and
should write only zeros to unmapped registers. Note that it is more
efficient to issue a new write command than to write the default
value to more than two consecutive reserved (or unmapped)
registers.
I7
A7
I6
A6
I5
A5
I4
A4
I3
A3
I2
A2
I1
A1
AD9553
LSB
I0
A0