AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 28

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9553
5.
Determine N, K, and R.
For f
and N = 3888, which satisfies the constraint on both N and
R, and yields FPFD = 1 MHz.
For f
373,248, K = 1, and R = 12,500. This choice, however,
violates the constraints on both N and R in Step 3.
A simple remedy is to divide both N and R by a common
factor. In this particular case, four is the greatest common
factor of N and R. Dividing by four leads to N = 93,312,
K = 1, and R = 3125 (K = 1), satisfying the constraint on
N and R, and yielding FPFD = 40 kHz. Note that to match
the values given in the Preset Frequencies section, FPFD
must be 16 kHz. To accomplish this, keep R = 3125, but
choose K = 2/5 (see Table 14). This changes N to 233,280,
which agrees with Table 16.
For f
As with the case for f
violates the constraints on both N and R in Step 3. Once
again, the greatest common factor of N and R is four,
leading to N = 85,536, K = 1, and R = 3125 (K = 1),
yielding FPFD = 40 kHz.
In summary, if choosing f
possible solution is
If one chooses f
that matches the tables in the Preset Frequencies section is
If choosing f
N = 342,144
K = 1
R = 12,500.
P
P
N = 85,536
R = 3,125
K = 1
FPFD = 40 kHz
P
P
N = 233,280
R = 3,125
K = 2/5
FPFD = 16 kHz
P
P
N = 3888
R = 125
K = 1
FPFD = 1 MHz
0
1
0
1
0
1
VCO
VCO
VCO
= 11
= 2
= 6
= 4
= 5
= 5
= 3421.44 MHz, an obvious solution is
= 3732.48 MHz, an obvious solution is N =
= 3888 MHz, an obvious solution is K = 1, R = 125,
VCO
VCO
= 3888 MHz, then a possible solution is
= 3732.48 MHz, then the solution set
VCO
= 3732.48 MHz, this choice
VCO
= 3421.44 MHz, then a
Rev. A | Page 28 of 44
6.
LOW DROPOUT (LDO) REGULATORS
The AD9553 is powered from a single 3.3 V supply and contains
on-chip LDO regulators for each function to eliminate the need
for external LDOs. To ensure optimal performance, each LDO
output should have a 0201-sized 0.47 μF capacitor connected
between its access pin and ground. In addition, double vias to
ground for these capacitors minimize the parasitic resistance and
inductance.
AUTOMATIC POWER-ON RESET
The AD9553 has an internal power-on reset circuit (see Figure 33).
At power-up, an 800 pF capacitor momentarily holds a Logic 0
at the active low input of the reset circuitry. This ensures that the
device is held in a reset state (~250 µs) until the capacitor charges
sufficiently via the 100 kΩ pull-up resistor and 200 kΩ series
resistor. Note that when using a low impedance source to drive
the RESET pin, be sure that the source is either tristate or Logic 0
at power-up. Otherwise, the device may not calibrate properly.
Provided an input reference signal is present at the REFA,
REFB, or XTAL pin, the device automatically performs a VCO
calibration during power-up. If the input reference signal is not
present, VCO calibration fails and the PLL does not lock. As
soon as an input reference signal is present, the user must reset
the device to initiate the automatic VCO calibration process.
Any change to the preset frequency selection pins requires the
user to reset the device. This is necessary to initiate the automatic
VCO calibration process.
If applicable, determine R
The value of R
from Step 5, as follows:
Given that f
R
R
R
XO
XO
XO
= 3125 (for R = 3125 and K = 2/5)
= 50 (for R = 125 and K = 1)
=
RESET




50
REF
f
×
= 125 MHz, the two results from Step 5 lead to
REF
XO
15
10
Figure 33. Power-On Reset
100kΩ
depends on the value of f
6







VDD
K
R
200kΩ
800pF



XO
, the XTAL divider value.
AD9553
CIRCUITRY
RESET
REF
, K, and R