AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 4

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9553
RESET PIN
Table 4.
Parameter
INPUT CHARACTERISTICS
MINIMUM PULSE WIDTH LOW
1
REFERENCE CLOCK INPUT CHARACTERISTICS
Table 5.
Parameter
DIFFERENTIAL INPUT
CMOS SINGLE-ENDED INPUT
×2 FREQUENCY MULTIPLIER
The RESET pin has a 100 kΩ internal pull-up resistor.
Input Frequency Range
Common-Mode Internally Generated
Differential Input Voltage Sensitivity
Differential Input Resistance
Differential Input Capacitance
Input Frequency Range
Input High Voltage
Input Low Voltage
Input Threshold Voltage
Input High Current
Input Low Current
Input Capacitance
Input Voltage High, V
Input Voltage Low, V
Input Current High, I
Input Current Low, I
Duty Cycle
Duty Cycle
Input Voltage
Pulse Width Low
Pulse Width High
Pulse Width Low
Pulse Width High
Pulse Width Low
Pulse Width High
INL
IL
INH
IH
1
Min
1.96
150
Min
0.008
613
250
1.6
1.6
0.64
0.64
0.008
1.62
2
2
Typ
0.3
31
Typ
692
5
3
1.0
0.04
0.03
3
Max
0.85
12.5
43
Max
250
710
769
200
0.52
125
Rev. A | Page 4 of 44
Unit
V
V
µA
µA
µs
Unit
MHz
MHz
mV
mV p-p
kΩ
pF
ns
ns
ns
ns
MHz
V
V
V
µA
µA
pF
ns
ns
MHz
Test Conditions/Comments
Tested with an active source driving the
Test Conditions/Comments
Assumes minimum LVDS input level and requires
bypassing of the divide-by-5 divider and ×2 multiplier
Use ac coupling to preserve the internal dc bias of the
differential input
Requires ac coupling; can accommodate single-ended
input by ac grounding unused input; the instantaneous
voltage on either pin must not exceed the 3.3 V dc supply
rails
Pulse width high and pulse width low specifications
establish the bounds for duty cycle
Up to 250 MHz
Up to 250 MHz
Beyond 250 MHz, up to 710 MHz
Beyond 250 MHz, up to 710 MHz
When ac coupling to the input receiver, the user must dc
bias the input to 1 V; the single-ended CMOS input is 3.3 V
compatible
Pulse width high and pulse width low establish the
bounds for duty cycle
To avoid excessive reference spurs, the ×2 multiplier
requires 48% to 52% duty cycle; reference clock input
frequencies greater than 125 MHz require the use of the
divide-by-5 divider
RESET
pin