AD9553/PCBZ Analog Devices Inc, AD9553/PCBZ Datasheet - Page 19

• Manufacturer Part Number: AD9553/PCBZ
• Description: Clock Translator Eval. Board
• Manufacturer: Analog Devices Inc

Specifications of AD9553/PCBZ

• Silicon Manufacturer: Analog Devices
• Silicon Core Number: AD9553
• Kit Application Type: Clock & Timing
• Application Sub Type: Clock Translator
• Peak Reflow Compatible (260 C): Yes
• Msl: MSL 3 - 168 Hours
• Rohs Compliant: Yes
• Development Tool Type: Hardware - Eval/Demo Board
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 16.
A3 to A0
0001 to 1100
1101
1110
1111
1
2
DEVICE CONTROL MODES
The AD9553 provides two modes of control: pin control and
register control. Pin control, via the frequency selection pins
(Ax and Yx) as described in the Preset Frequencies section, is
the simplest. Typically, pin control is for applications requiring
only a single set of operating parameters (assuming that one of
the options available via the frequency selection pins provides
the parameters that satisfy the application requirements). Register
control is typically for applications that require the flexibility to
program different operating parameters from time to time, or
for applications that require parameters not available with any
of the pin control options. The block diagram (see Figure 28)
shows how the SPI and pin control modes interact.
The SPI/OM[2:0] label in Figure 28 refers to Pin 12, Pin 13, and
Pin 14 of the AD9553. Furthermore, the SPI mode signal is Logic 1
when Pin A3 to Pin A0 = 0000 and/or Pin Y5 to Pin Y0 = 000000;
otherwise, it is Logic 0. The SPI/OM[2:0] pins serve double
duty (as either SPI pins or output mode control pins). A mux
(controlled by the SPI mode signal) selects whether the three
signals associated with the SPI/OM[2:0] pins connect to the
output mode control decoder or to the SPI controller. Note
that the SPI mode signal originates from the frequency selec-
tion pins decoder.
To enable communication with the SPI controller (SPI mode),
the user must apply the appropriate logic pattern to the frequency
selection pins (A3 to A0 = 0000 and/or Y5 to Y0 = 000000).
PLL feedback divider value (decimal).
Charge pump register value (decimal). Multiply by 3.5 µA to yield I
Pin Configuration vs. PLL Feedback Divider (N) and Charge Pump Value (CP)
Y5 to Y0
000001 to 010101
010110 to 011011
011100 to 100001
100010 to 100110
100111 to 101011
101100
101101 to 111111
000001 to 101100
101101 to 110010
110010 to 111111
000001 to 110010
110011
110100 to 111110
111111
000001 to 010101
010110 to 011011
011100 to 100001
100010 to 100110
100111 to 101011
101100
101101 to 111111
CP
.
Rev. A | Page 19 of 44
Note that as long as the frequency selection pins are set to invoke
SPI mode, the user cannot establish output mode control via the
output mode control decoder. Conversely, when the frequency
selection pins are set to anything other than SPI mode, the user
cannot communicate with the device via the SPI controller.
In Figure 28, note that some of the functions internal to the
AD9553 are controlled by function bits that originate either
from the two pin decoders or from within the register map.
Specifically, each function receives its function bits from a
function mux; and each function mux, in turn, receives its
control signal from a single enable SPI control bit in the
register map.
Be aware that the default values within the register map are such
that all enable SPI control bits are Logic 0. Thus, the default state of
the device is such that each function mux selects the pin decoders
(not the register map) as the source for all control functions.
In order to switch a function mux so that it selects function bits
from the register map, the user must first set the frequency selec-
tion pins to SPI mode. Then, write a Logic 1 to the appropriate
enable SPI control bit in the register map. Be aware that the
function mux routes the function bits in the register map to
the selected function the instant that the enable SPI control
bit becomes Logic 1. Thus, it is a good idea to program the
function bits to the desired state prior to writing Logic 1 to
the corresponding enable SPI control bit.
N
230,400
234,375
233,280
230,400
225,000
231,600
Undefined
Undefined
1512
Undefined
Undefined
768
Undefined
2400
276,480
281,250
279,936
276,480
270,000
277,920
Undefined
1
CP
121
121
121
121
121
121
Undefined
Undefined
255
Undefined
Undefined
121
Undefined
121
145
145
145
145
145
145
Undefined
AD9553
2