ISP1508AET NXP Semiconductors, ISP1508AET Datasheet - Page 12

• Manufacturer Part Number: ISP1508AET
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1508AET

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283548118 ISP1508AET-T

NXP Semiconductors
ISP1508A_ISP1508B_1
Product data sheet
7.14 STP
7.15 NXT
7.16 CLOCK
7.17 GND
ULPI stop input pin. Synchronous to the rising edge of CLOCK. The link must assert STP
to signal the end of a USB transmit packet or a register write operation. When DIR is
asserted, the link can optionally assert STP for one cycle to abort the ISP1508, causing it
to de-assert DIR in the next clock cycle.
ULPI next data output pin. Synchronous to the rising edge of CLOCK. The ISP1508 holds
NXT at LOW, by default. When DIR is LOW and the link is sending data to the ISP1508,
NXT will be asserted to notify the link to provide the next data byte. When DIR is HIGH
and the ISP1508 is sending data to the link, NXT will be asserted to notify the link that
another valid byte is on the bus. NXT is not used for register read data or the RXCMD
status update.
This pin can be 3-stated when the CHIP_SEL pin is not active.
A 60 MHz interface clock to synchronize the ULPI bus. In SDR mode, all ULPI pins are
synchronous to the rising edge of CLOCK. In DDR mode, DATA[3:0] are the only interface
pins that are synchronous to both the rising and falling edges of CLOCK. All other pins are
synchronous to the rising edge of CLOCK only, including DIR, NXT and STP.
The ISP1508 outputs 60 MHz clock when:
Global ground signal. To ensure the correct operation of the ISP1508, GND must be
soldered to the cleanest available ground.
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A crystal is attached between the XTAL1 and XTAL2 pins.
A clock is driven into the XTAL1 pin, with the XTAL2 pin left unconnected.
Rev. 01 — 14 August 2007
ISP1508A; ISP1508B
ULPI HS USB transceiver
© NXP B.V. 2007. All rights reserved.
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