ISP1508AET NXP Semiconductors, ISP1508AET Datasheet - Page 53

• Manufacturer Part Number: ISP1508AET
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1508AET

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283548118 ISP1508AET-T

NXP Semiconductors
Table 32.
ISP1508A_ISP1508B_1
Product data sheet
Bit
7
6
5
4
3
2
1
0
Symbol
INTF_PROT_DIS
IND_PASSTHRU
IND_COMPL
-
CLOCK_SUSPENDM
CARKIT_MODE
3PIN_FSLS_SERIAL
6PIN_FSLS_SERIAL
Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description
11.4 OTG Control register
This register controls various OTG functions of the ISP1508. The bit allocation of the OTG
Control register is given in
Description
Interface Protect Disable: Controls circuitry built into the ISP1508 to protect the ULPI
interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1508
will automatically detect when the link stops driving STP.
0b — Enables the interface protect circuit. The ISP1508 attaches a weak pull-up resistor
on STP. If STP is unexpectedly HIGH, the ISP1508 attaches weak pull-down resistors on
DATA[7:0], protecting data inputs.
1b — Disables the interface protect circuit, detaches weak pull-down resistors on
DATA[7:0], and a weak pull-up resistor on STP.
Indicator Pass-through: Controls whether the complement output is qualified with the
internal A_VBUS_VLD comparator before being used in the V
0b — The complement output signal is qualified with the internal A_VBUS_VLD
comparator.
1b — The complement output signal is not qualified with the internal A_VBUS_VLD
comparator.
Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the
complement output.
0b — The ISP1508 will not invert the FAULT signal.
1b — The ISP1508 will invert the FAULT signal.
reserved
Clock Suspend LOW: Active LOW clock suspend.
Powers down the internal clock circuitry only. By default, the clock will not be powered in
6-pin serial mode or 3-pin serial mode.
Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set
to logic 1, otherwise this bit is ignored.
0b — Clock will not be powered in 3-pin or 6-pin serial mode, or UART mode.
1b — Clock will be powered in 3-pin and 6-pin serial mode, or UART mode.
Carkit Mode: Changes the ULPI interface to the carkit interface (UART mode). Bits
TXD_EN and RXD_EN in the Carkit Control register must change as well. The PHY must
automatically clear this bit when carkit mode is exited.
0b — Disable carkit mode.
1b — Enable carkit mode.
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial
interface. The ISP1508 will automatically clear this bit when 3-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface.
1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.
6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial
interface. The ISP1508 will automatically clear this bit when 6-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface.
1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.
Rev. 01 — 14 August 2007
Table
33.
ISP1508A; ISP1508B
ULPI HS USB transceiver
BUS
state in RXCMD.
© NXP B.V. 2007. All rights reserved.
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