ISP1508AET NXP Semiconductors, ISP1508AET Datasheet - Page 14

• Manufacturer Part Number: ISP1508AET
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1508AET

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935283548118 ISP1508AET-T

NXP Semiconductors
ISP1508A_ISP1508B_1
Product data sheet
8.4 Voltage regulator
8.5 Crystal oscillator and PLL
8.6 UART buffer
For details on controlling resistor settings, see
The ISP1508 contains a built-in voltage regulator that conditions the V
inside the ISP1508. The voltage regulator:
The ISP1508 has a built-in crystal oscillator and a Phase-Locked Loop (PLL) for clock
generation. When a crystal is in use, the built-in crystal oscillator generates a square wave
clock for internal use. A square wave clock of the same frequency can also be driven
directly into the XTAL1 pin. Using an existing square wave clock can save the cost of a
crystal and also reduce the board space. The crystal or clock frequencies supported are
13 MHz, 19.2 MHz, 24 MHz and 26 MHz.
The PLL takes the square wave clock from the crystal oscillator and multiplies or divides it
into various frequencies for internal use.
The PLL produces the following frequencies, irrespective of the clock source:
The UART buffer includes circuits to support the transparent UART signaling between the
DATA0 or DATA1 pin and the DM or DP pin.
When the ISP1508 is put into UART mode, it acts as a voltage level shifter between the
following pins:
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High-speed disconnect detector
45
1.5 k pull-up resistor on DP
15 k bus terminations on DP and DM
Supports input supply range 3.0 V < V
Can be supplied from a battery with the preceding voltage range.
Supplies internal digital circuitry with 1.8 V and analog circuitry with 3.3 V or 2.7 V.
In USB mode, automatically bypasses the internal 3.3 V regulator when V
the internal analog circuitry directly draws power from the V
bypass switch will be disabled.
Will be shut down when V
active.
1.5 MHz for low-speed USB data
12 MHz for full-speed USB data
60 MHz clock for the ULPI interface controller
480 MHz for high-speed USB data
Other internal frequencies for data conversion and data recovery
From DATA0 (V
high-speed bus terminations on DP and DM
CC(I/O)
Rev. 01 — 14 August 2007
level) to DM (2.7 V level) for the UART TXD signaling path.
CC(I/O)
is not present or when the CHIP_SEL pin is not
CC
ISP1508A; ISP1508B
< 4.5 V.
Table
14.
ULPI HS USB transceiver
CC
pin. In UART mode, the
CC
© NXP B.V. 2007. All rights reserved.
supply for use
CC
< 3.5 V,
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