LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 137

• Manufacturer Part Number: LFE2M20E-6FN484C
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-6FN484C

• Package: 484FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 1246208

Lattice Semiconductor
LFE2-6E/SE and LFE2-12E/SE Logic Signal Connections: 256 fpBGA (Cont.)
Number
VCCIO
VCCIO
VCCIO
VCCIO
GND
GND
GND
GND
GND
GND
Ball
M13
M16
G16
G15
N14
N13
N15
P15
N16
R14
P14
R16
P16
K11
K14
K13
K15
K16
H12
H13
H15
H16
H11
L12
L15
L14
L16
L10
L13
J16
J15
J14
J13
J12
J11
RLM0_PLLCAP
PROGRAMN
Function
Ball/Pad
GNDIO8
GNDIO8
GNDIO8
GNDIO3
GNDIO3
GNDIO2
VCCIO8
VCCIO8
VCCIO3
VCCIO3
PR30B
PR29B
PR30A
PR28B
PR29A
PR28A
PR27B
PR26A
PR27A
PR25B
PR26B
PR25A
PR24B
PR24A
PR21B
PR21A
PR20B
PR20A
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR13B
PR13A
DONE
CFG1
CFG0
CCLK
INITN
Bank
LFE2-6E/SE
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
-
-
-
-
-
-
RLM0_GDLLC_IN_A**
RLM0_GPLLC_IN_A**
RLM0_GPLLT_IN_A**
RLM0_GDLLT_IN_A**
RLM0_GPLLC_FB_A
RLM0_GDLLC_FB_A
RLM0_GDLLT_FB_A
RLM0_GPLLT_FB_A
PCLKC2_0/RDQ10
PCLKT2_0/RDQ10
Dual Function
D0/SPIFASTN
DOUT/CSON
DI/CSSPI0N
BUSY/SISPI
PCLKC3_0
PCLKT3_0
D7/SPID0
VREF2_3
VREF1_3
WRITEN
CS1N
CSN
D1
D2
D3
D6
D4
D5
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
C
T
T
T
T
T
4-34
RLM0_PLLCAP
PROGRAMN
Function
Ball/Pad
GNDIO8
GNDIO8
GNDIO8
GNDIO3
GNDIO3
GNDIO2
VCCIO8
VCCIO8
VCCIO3
VCCIO3
PR30B
PR29B
PR30A
PR28B
PR29A
PR28A
PR27B
PR26A
PR27A
PR25B
PR26B
PR25A
PR24B
PR24A
PR21B
PR21A
PR20B
PR20A
PR18B
PR18A
PR17B
PR17A
PR16B
PR16A
PR15B
PR15A
PR13B
PR13A
DONE
CFG1
CFG0
CCLK
INITN
LatticeECP2/M Family Data Sheet
Bank
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
-
-
-
-
-
-
LFE2-12E/SE
RLM0_GPLLC_IN_A**
RLM0_GDLLC_IN_A**
RLM0_GPLLT_IN_A**
RLM0_GDLLT_IN_A**
RLM0_GDLLC_FB_A
RLM0_GPLLC_FB_A
RLM0_GPLLT_FB_A
RLM0_GDLLT_FB_A
PCLKC2_0/RDQ10
PCLKT2_0/RDQ10
Dual Function
D0/SPIFASTN
DOUT/CSON
DI/CSSPI0N
BUSY/SISPI
PCLKC3_0
PCLKT3_0
D7/SPID0
VREF2_3
VREF1_3
WRITEN
CS1N
Pinout Information
CSN
D1
D2
D3
D6
D4
D5
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
T