LFE2M20E-6FN484C LATTICE SEMICONDUCTOR, LFE2M20E-6FN484C Datasheet - Page 3

• Manufacturer Part Number: LFE2M20E-6FN484C
• Description: FPGA LatticeECP2M Family 19000 Cells 90nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LFE2M20E-6FN484C

• Package: 484FBGA
• Family Name: LatticeECP2M
• Device Logic Units: 19000
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 304
• Ram Bits: 1246208

Lattice Semiconductor
Table 1-2. LatticeECP2M (Including “S-Series”) Family Selection
Introduction
The LatticeECP2/M family of FPGA devices is optimized to deliver high performance features such as advanced
DSP blocks, high speed SERDES (LatticeECP2M family only) and high speed source synchronous interfaces in an
economical FPGA fabric. This combination was achieved through advances in device architecture and the use of
90nm technology.
The LatticeECP2/M FPGA fabric is optimized with high performance and low cost in mind. The LatticeECP2/M
devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), Delay Locked
Loops (DLLs), pre-engineered source synchronous I/O support, enhanced sysDSP blocks and advanced configu-
ration support, including encryption (“S” versions only) and dual boot capabilities.
The LatticeECP2M device family features high speed SERDES with PCS. These high jitter tolerance and low trans-
mission jitter SERDES with PCS blocks can be configured to support an array of popular data protocols including
PCI Express, Ethernet (1GbE and SGMII), OBSAI and CPRI. Transmit Pre-emphasis and Receive Equalization
settings make SERDES suitable for chip to chip and small form factor backplane applications.
The Lattice Diamond™ and ispLEVER
implemented using the LatticeECP2/M FPGA family. Synthesis library support for LatticeECP2/M is available for
popular logic synthesis tools. The Diamond and ispLEVER tools use the synthesis tool output along with the con-
straints from its floor planning tools to place and route the design in the LatticeECP2/M device. The Diamond and
ispLEVER tools extract the timing from the routing and back-annotates it into the design for timing verification.
Lattice provides many pre-engineered IP (Intellectual Property) modules for the LatticeECP2/M family. By using
these IP cores as standardized blocks, designers are free to concentrate on the unique aspects of their design,
increasing their productivity.
LUTs (K)
sysMEM Blocks (18kb)
Embedded Memory (Kbits)
Distributed Memory (Kbits)
sysDSP Blocks
18x18 Multipliers
GPLL+SPLL+DLL
Maximum Available I/O
Packages and SERDES / I/O Combinations
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
1152-ball fpBGA (35 x 35 mm)
Device
ECP2M20
4 / 140
4 / 304
2+6+2
1217
304
19
66
41
24
6
®
design software from Lattice allow large complex designs to be efficiently
ECP2M35
4 / 303
4 / 410
2+6+2
4 / 140
2101
114
410
34
71
32
8
1-2
ECP2M50
4 / 270
8 / 372
8 / 410
2+6+2
4147
225
101
410
48
22
88
LatticeECP2/M Family Data Sheet
ECP2M70
16 / 416
16 / 436
2+6+2
4534
246
145
436
67
24
96
Introduction
ECP2M100
16 / 416
16 / 520
2+6+2
5308
288
202
168
520
95
42