16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY

PIC24HJ64GP510A-E/PF

Manufacturer Part NumberPIC24HJ64GP510A-E/PF
Description16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
ManufacturerMicrochip Technology
SeriesPIC® 24H
PIC24HJ64GP510A-E/PF datasheets
 

Specifications of PIC24HJ64GP510A-E/PF

Core ProcessorPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDTNumber Of I /o85
Program Memory Size64KB (22K x 24)Program Memory TypeFLASH
Ram Size8K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 32x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CPackage / Case100-TQFP, 100-VQFP
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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3.6.4
CodeGuard™ SECURITY
CONFIGURATION BITS
The FBS, FSS and FGS Configuration registers are
special Configuration registers that control the size and
level of code protection for the Boot Segment, Secure
Segment and General Segment, respectively. For each
segment, two main forms of code protection are
provided. One form prevents code memory from being
written (write protection), while the other prevents code
memory from being read (read protection).
BWRP, SWRP and GWRP bits control write protection
and BSS<2:0>, SSS<2:0> and GSS<1:0> bits control
read protection. The Chip Erase ERASEB command
sets all the code protection bits to ‘1’, which allows the
device to be programmed.
When write protection is enabled, any programming
operation to code memory will fail. When read
protection is enabled, any read from code memory will
cause a ‘0x0’ to be read, regardless of the actual
contents of code memory. Since the programming
executive always verifies what it programs, attempting
to program code memory with read protection enabled
will also result in failure.
It is imperative that all code protection bits are ‘1’ while
the device is being programmed and verified. Only after
the device is programmed and verified should any of
the above bits be programmed to ‘0’.
In addition to code memory protection, a part of Data
RAM can be configured to be accessible only by code
resident in the Boot Segment and/or Secure Segment.
The
sizes
of
these
“reserved”
user-configurable, using the RBS<1:0> and RSS<1:0>
bits.
Note:
All bits in the FBS, FSS and FGS
Configuration registers can only be
programmed to a value of ‘0’. Bulk Erase
and Segment Erase operations (depend-
ing on the segment) are the only way to
reprogram code-protect bits from ON (‘0’)
to OFF (‘1’).
DS70152H-page 22
3.6.5
BENEFIT OF USER UNIT ID
The dsPIC33F/PIC24H devices provide up to four 8-bit
Configuration registers (FUID0 through FUID3) for the
user to store product-specific information, such as unit
serial numbers and other product manufacturing data.
3.7
Exiting Enhanced ICSP Mode
Exiting Program/Verify mode is done by removing V
from MCLR, as illustrated in
requirement for exit is that an interval P16 should
elapse between the last clock and program signals on
PGCx and PGDx before removing V
FIGURE 3-6:
MCLR
V
DD
PGDx
PGCx
sections
are
IH
Figure
3-6. The only
.
IH
EXITING ENHANCED
ICSP™ MODE
P16
P17
V
IH
V
IH
PGDx = Input
© 2010 Microchip Technology Inc.