PIC24HJ64GP510A-E/PF Microchip Technology, PIC24HJ64GP510A-E/PF Datasheet - Page 53

16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY

PIC24HJ64GP510A-E/PF

Manufacturer Part Number
PIC24HJ64GP510A-E/PF
Description
16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 24Hr

Specifications of PIC24HJ64GP510A-E/PF

Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
64KB (22K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
6.2
Programming Verification
After
the
programming
executive
programmed to executive memory using ICSP, it must
be verified. Verification is performed by reading out the
contents of executive memory and comparing it with
the image of the programming executive stored in the
programmer.
TABLE 6-2:
READING EXECUTIVE MEMORY
Command
Data
(Binary)
(Hex)
Step 1: Exit the Reset vector.
0000
040200
GOTO
0000
040200
GOTO
0000
000000
NOP
Step 2: Initialize TBLPAG and the read pointer (W6) for TBLRD instruction.
0000
200800
MOV
0000
880190
MOV
0000
EB0300
CLR
Step 3: Initialize the write pointer (W7) and store the next four locations of code memory to W0:W5.
0000
EB0380
CLR
0000
000000
NOP
0000
BA1B96
TBLRDL
0000
000000
NOP
0000
000000
NOP
0000
BADBB6
TBLRDH.B
0000
000000
NOP
0000
000000
NOP
0000
BADBD6
TBLRDH.B
0000
000000
NOP
0000
000000
NOP
0000
BA1BB6
TBLRDL
0000
000000
NOP
0000
000000
NOP
0000
BA1B96
TBLRDL
0000
000000
NOP
0000
000000
NOP
0000
BADBB6
TBLRDH.B
0000
000000
NOP
0000
000000
NOP
0000
BADBD6
TBLRDH.B
0000
000000
NOP
0000
000000
NOP
0000
BA0BB6
TBLRDL
0000
000000
NOP
0000
000000
NOP
© 2010 Microchip Technology Inc.
Reading the contents of executive memory can be
performed using the same technique described in
has
been
Section 5.8 “Reading Code
for reading executive memory is shown in
Note that in Step 2, the TBLPAG register is set to 0x80,
such that executive memory may be read.
Description
0x200
0x200
#0x80, W0
W0, TBLPAG
W6
W7
[W6], [W7++]
[W6++], [W7++]
[++W6], [W7++]
[W6++], [W7++]
[W6], [W7++]
[W6++], [W7++]
[++W6], [W7++]
[W6++], [W7]
Memory”. A procedure
Table
6-2.
DS70152H-page 53

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