16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY

PIC24HJ64GP510A-E/PF

Manufacturer Part NumberPIC24HJ64GP510A-E/PF
Description16 Bit MCU 40MIPS 64KB FLASH 100 TQFP 14x14x1mm TRAY
ManufacturerMicrochip Technology
SeriesPIC® 24H
PIC24HJ64GP510A-E/PF datasheets
 


Specifications of PIC24HJ64GP510A-E/PF

Core ProcessorPICCore Size16-Bit
Speed40 MIPsConnectivityCAN, I²C, IrDA, LIN, SPI, UART/USART
PeripheralsBrown-out Detect/Reset, DMA, POR, PWM, WDTNumber Of I /o85
Program Memory Size64KB (22K x 24)Program Memory TypeFLASH
Ram Size8K x 8Voltage - Supply (vcc/vdd)3 V ~ 3.6 V
Data ConvertersA/D 32x10b/12bOscillator TypeInternal
Operating Temperature-40°C ~ 125°CPackage / Case100-TQFP, 100-VQFP
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Page 38/84

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TABLE 5-4:
SERIAL INSTRUCTION EXECUTION FOR BULK ERASING CODE MEMORY
Command
Data
(Binary)
(Hex)
Step 1: Exit the Reset vector.
0000
040200
GOTO
0000
040200
GOTO
0000
000000
NOP
Step 2: Set the NVMCON to erase all program memory.
0000
2404FA
MOV
0000
883B0A
MOV
Step 3: Initiate the erase cycle.
0000
A8E761
BSET
0000
000000
NOP
0000
000000
NOP
0000
000000
NOP
0000
000000
NOP
Step 4: Wait for Bulk Erase operation to complete and make sure WR bit is clear.
Externally time ‘P11’ msec (see
Timing
complete.
5.6
Writing Code Memory
The procedure for writing code memory is similar to the
procedure for writing the Configuration registers,
except that 64 instruction words are programmed at a
time. To facilitate this operation, working registers,
W0:W5, are used as temporary holding registers for the
data to be programmed.
Table 5-5
shows the ICSP programming details,
including the serial pattern with the ICSP command
code, which must be transmitted Least Significant bit
first using the PGCx and PGDx pins (see
In Step 1, the Reset vector is exited. In Step 2, the
NVMCON register is initialized for programming of
code memory. In Step 3, the 24-bit starting destination
address for programming is loaded into the TBLPAG
register and W7 register. The upper byte of the
starting destination address is stored in TBLPAG and
the lower 16 bits of the destination address are stored
in W7.
To minimize the programming time, the same packed
instruction format that the programming executive uses
is utilized (see
Figure
4-4). In Step 4, four packed
instruction words are stored in working registers,
W0:W5, using the MOV instruction and the read pointer,
W6, is initialized. The contents of W0:W5 holding the
packed instruction word data are illustrated in
Figure
5-7. In Step 5, eight TBLWT instructions are used
to copy the data from W0:W5 to the write latches of
code memory. Since code memory is programmed 64
instruction words at a time, Steps 4 and 5 are repeated
16 times to load all the write latches (Step 6).
DS70152H-page 38
Description
0x200
0x200
#0x404F, W10
W10, NVMCON
NVMCON, #WR
Section 8.0 “AC/DC Characteristics and
Requirements”) to allow sufficient time for the Bulk Erase operation to
After the write latches are loaded, programming is
initiated by writing to the NVMCON register in Steps 7
and 8. In Step 9, the internal PC is reset to 0x200. This is
a precautionary measure to prevent the PC from
incrementing into unimplemented memory when large
devices are being programmed. Lastly, in Step 10,
Steps 3-9 are repeated until all of code memory is
programmed.
FIGURE 5-7:
Figure
5-2).
15
W0
W1
MSB1
W2
W3
W4
MSB3
W5
PACKED INSTRUCTION
WORDS IN W0:W5
8
7
0
LSW0
MSB0
LSW1
LSW2
MSB2
LSW3
© 2010 Microchip Technology Inc.