MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 209

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

6.8.1.1
6.8.1.2
Instructions that use this addressing mode either have no operands or all operands are in internal XGATE
registers:.
Examples
6.8.1.3
Operands for immediate mode instructions are included in the instruction stream and are fetched into the
instruction queue along with the rest of the 16 bit instruction. The ’#’ symbol is used to indicate an
immediate addressing mode operand. This address mode is used for semaphore instructions.
Examples:
Freescale Semiconductor
RD
RD.L
RD.H
RS, RS1, RS2
RS.L, RS1.L, RS2.L
RS.H, RS1.H, RS2.H
RB
RI
RI+
–RI
BRK
RTS
CSEM
SSEM
Naming Conventions
Inherent Addressing Mode (INH)
Immediate 3-Bit Wide (IMM3)
Even though register R1 is intended to be used as a pointer to the variable
segment, it may be used as a general purpose data register as well.
Selecting R0 as destination register will discard the result of the instruction.
Only the condition code register will be updated
#1
#3
; Unlock semaphore 1
; Lock Semaphore 3
Destination register, allowed range is R0–R7
Low byte of the destination register, bits [7:0]
High byte of the destination register, bits [15:8]
Source register, allowed range is R0–R7
Low byte of the source register, bits [7:0]
High byte of the source register, bits[15:8]
Base register for indexed addressing modes, allowed
range is R0–R7
Offset register for indexed addressing modes with
register offset, allowed range is R0–R7
Offset register for indexed addressing modes with
register offset and post-increment,
Allowed range is R0–R7 (R0+ is equivalent to R0)
Offset register for indexed addressing modes with
register offset and pre-decrement,
Allowed range is R0–R7 (–R0 is equivalent to R0)
MC9S12XDP512 Data Sheet, Rev. 2.21
NOTE
Chapter 6 XGATE (S12XGATEV2)
209