MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 98

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.4
2.4.1
2.4.1.1
The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased
flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers
a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,...
126,128 based on the SYNR register.
The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on
the difference between the output frequency and the target frequency. The PLL can change between
acquisition and tracking modes either automatically or manually.
The VCO has a minimum operating frequency, which corresponds to the self clock mode frequency f
98
EXTAL
XTAL
supplied by:
Functional Description
Functional Blocks
Phase Locked Loop (PLL)
V
V
CONSUMPTION
Although it is possible to set the two dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1), Bus Clock = PLLCLK / 2
DDPLL
DD
OSCILLATOR
REDUCED
/V
SS
/V
SSPLL
OSCCLK
MONITOR
CRYSTAL
PLLCLK
Figure 2-16. PLL Functional Diagram
MC9S12XDP512 Data Sheet, Rev. 2.21
PROGRAMMABLE
REFDV <5:0>
REFERENCE
DIVIDER
=
PROGRAMMABLE
2 OSCCLK
SYN <5:0>
DIVIDER
CAUTION
LOOP
REFERENCE
FEEDBACK
----------------------------------- -
REFDV
SYNR
DETECTOR
DETECTOR
FILTER
LOOP
PHASE
LOCK
PDET
+
+
1
1
V
DDPLL
DOWN
UP
LOCK
CPUMP
XFC
PIN
Freescale Semiconductor
V
DDPLL
/V
SSPLL
VCO
PLLCLK
SCM
.