MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 483
MC9S12XDT512CAA
Manufacturer Part Number
MC9S12XDT512CAA
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDT512CAA.pdf
(1348 pages)
Specifications of MC9S12XDT512CAA
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
59
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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11.3.2.2
Read: Anytime, if AMAP = 0.
Write: Anytime, if AMAP = 0.
Freescale Semiconductor
SCISWAI
LOOPS
Reset
WAKE
RSRC
Field
M
7
6
5
4
3
W
R
LOOPS
Loop Select Bit — LOOPS enables loop operation. In loop operation, the RXD pin is disconnected from the SCI
and the transmitter output is internally connected to the receiver input. Both the transmitter and the receiver must
be enabled to use the loop function.
0 Normal operation enabled
1 Loop operation enabled
The receiver input is determined by the RSRC bit.
SCI Stop in Wait Mode Bit — SCISWAI disables the SCI in wait mode.
0 SCI enabled in wait mode
1 SCI disabled in wait mode
Receiver Source Bit — When LOOPS = 1, the RSRC bit determines the source for the receiver shift register
input. See
0 Receiver input internally connected to transmitter output
1 Receiver input connected externally to transmitter
Data Format Mode Bit — MODE determines whether data characters are eight or nine bits long.
0 One start bit, eight data bits, one stop bit
1 One start bit, nine data bits, one stop bit
Wakeup Condition Bit — WAKE determines which condition wakes up the SCI: a logic 1 (address mark) in the
most significant bit position of a received data character or an idle condition on the RXD pin.
0 Idle line wakeup
1 Address mark wakeup
SCI Control Register 1 (SCICR1)
0
7
This register is only visible in the memory map if AMAP = 0 (reset
condition).
Table
SCISWAI
0
6
11-4.
TNP[1:0]
Figure 11-5. SCI Control Register 1 (SCICR1)
11
10
01
00
Table 11-2. IRSCI Transmit Pulse Width
Table 11-3. SCICR1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
RSRC
0
5
NOTE
M
0
4
Narrow Pulse Width
Description
WAKE
1/32
1/16
3/16
1/4
Chapter 11 Serial Communication Interface (S12SCIV5)
0
3
ILT
0
2
PE
0
1
PT
0
0
483
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