MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 455

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

10.3.3.4
This register defines the local priority of the associated message buffer. The local priority is used for the
internal prioritization process of the MSCAN and is defined to be highest for the smallest binary number.
The MSCAN implements the following internal prioritization mechanisms:
In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.
Read: Anytime when TXEx flag is set (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
“MSCAN Transmit Buffer Selection Register
Write: Anytime when TXEx flag is set (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
“MSCAN Transmit Buffer Selection Register
10.3.3.5
If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see
Freescale Semiconductor
•
•
Reset:
All transmission buffers with a cleared TXEx flag participate in the prioritization immediately
before the SOF (start of frame) is sent.
The transmission buffer with the lowest local priority field wins the prioritization.
W
R
Transmit Buffer Priority Register (TBPR)
Time Stamp Register (TSRH–TSRL)
PRIO7
0
7
DLC3
0
0
0
0
0
0
0
0
1
Figure 10-36. Transmit Buffer Priority Register (TBPR)
PRIO6
0
6
DLC2
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
1
1
1
1
0
Table 10-33. Data Length Codes
Data Length Code
PRIO5
0
5
Section 10.3.2.7, “MSCAN Transmitter Flag Register
Section 10.3.2.7, “MSCAN Transmitter Flag Register
(CANTBSEL)”).
(CANTBSEL)”).
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
PRIO4
DLC1
0
4
0
0
1
1
0
0
1
1
0
PRIO3
3
0
DLC0
0
1
0
1
0
1
0
1
0
PRIO2
0
2
Data Byte
Count
PRIO1
0
1
2
3
4
5
6
7
8
Section 10.3.2.11,
Section 10.3.2.11,
Section 10.3.2.1,
0
1
PRIO0
0
0
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