MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 927

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

EDIV[1:0]
NCLKX2
IRQEN
Reset
IRQE
Field
23.0.5.14 IRQ Control Register (IRQCR)
Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
Field
1–0
6
7
6
W
R
IRQE
No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed
rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other
operating modes.
0 ECLKX2 is enabled
1 ECLKX2 is disabled
Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin. The
usage of the bits is shown in
programmed in all other operating modes.
IRQ Select Edge Sensitive Only
Special modes: Read or write anytime.
Normal and emulation modes: Read anytime, write once.
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
External IRQ Enable
Read or write anytime.
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
7
0
IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
= Unimplemented or Reserved
IRQEN
1
6
Table 23-16. ECLKCTL Field Descriptions (continued)
EDIV[1:0]
Table 23-17. Free-Running ECLK Clock Rate
Figure 23-16. IRQ Control Register (IRQCR)
00
01
10
11
Table 23-18. IRQCR Field Descriptions
Table
5
0
0
ECLK = Bus clock rate
ECLK = Bus clock rate divided by 2
ECLK = Bus clock rate divided by 3
ECLK = Bus clock rate divided by 4
23-17. Divider is always disabled in emulation modes and active as
Rate of Free-Running ECLK
0
0
4
Description
Description
3
0
0
0
0
2
1
0
0
0
0
0