MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 793

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

21.4.2
Internal visibility allows the observation of the internal MCU address and data bus as well as the
determination of the access source and the CPU pipe (queue) status through the external bus interface.
Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal
CPU and BDM accesses are made visible on the external bus interface, except those to BDM firmware and
BDM registers.
Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see
Table
show the type of access. External read data are also visible on IVDx.
21.4.2.1
The access source (bus master) can be determined from the external bus control signals ACC[2:0] as
shown in
The CPU instruction queue status (execution-start and data-movement information) is brought out as
IQSTAT[3:0] signals. For decoding of the IQSTAT values, refer to the S12X_CPU section.
21.4.2.2
A bus access lasts 1 ECLK cycle. In case of a stretched external access (emulation expanded mode), up to
an infinite amount of ECLK cycles may be added. ADDRx values will only be shown in ECLK high
phases, while ACCx, IQSTATx, and IVDx values will only be presented in ECLK low phases.
Based on this multiplex timing, ACCx are only shown in the current (first) access cycle. IQSTATx and
(for read accesses) IVDx follow in the next cycle. If the access takes more than one bus cycle, ACCx
display NULL (0x000) in the second and all following cycles of the access. IQSTATx display NULL
(0x0000) from the third until one cycle after the access to indicate continuation.
The resulting timing pattern of the external bus signals is outlined in the following tables for read, write
and interleaved read/write accesses. Three examples represent different access lengths of 1, 2, and n–1 bus
cycles. Non-shaded bold entries denote all values related to Access #0.
Freescale Semiconductor
21-11), internal writes on ADDRx and DATAx (see
Table
Internal Visibility
Access Source and Instruction Queue Status Signals
Emulation Modes Timing
21-8.
1
2
Invalid IVD brought out in read cycles
Denotes also accesses to BDM firmware and BDM registers (IQSTATx are
‘XXXX’ and R/W = 1 in these cases)
Table 21-8. Determining Access Source from Control Signals
101, 110, 111
ACC[2:0]
000
001
010
011
100
MC9S12XDP512 Data Sheet, Rev. 2.21
Repetition of previous access cycle
CPU access
BDM access
XGATE PRR access
No access
Reserved
2
Access Description
Table 21-12
1
Chapter 21 External Bus Interface (S12XEBIV2)
to
Table
21-14). R/W and LSTRB
Table 21-9
to
795