MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 946

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.47 Port H Input Register (PTIH)
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to detect
overload or short circuit conditions on output pins.
23.0.5.48 Port H Data Direction Register (DDRH)
Read: Anytime.
Write: Anytime.
This register configures each port H pin as either input or output.
If the associated routed SPI module is enabled this register has no effect on the pins.
The SCI forces the I/O state to be an output for each port line associated with an enabled output ( TXD4).
It also forces the I/O state to be an input for each port line associated with an enabled input ( RXD4). In
those cases the data direction bits will not change.
If a SPI module is enabled, the SPI determines the pin direction. Refer to SPI section for details.
The DDRH bits revert to controlling the I/O direction of a pin when the associated peripheral modules are
disabled.
948
Reset
Reset
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
W
associated pin values.
W
R
R
1
DDRH7
PTIH7
—
0
7
7
= Unimplemented or Reserved
DDRH6
PTIH6
—
0
6
6
Figure 23-50. Port H Data Direction Register (DDRH)
Figure 23-49. Port H Input Register (PTIH)
DDRH5
MC9S12XDP512 Data Sheet, Rev. 2.21
PTIH5
—
0
5
5
DDRH4
PTIH4
—
0
4
4
DDRH3
PTIH3
—
0
3
3
DDRH2
PTIH2
—
0
2
2
DDRH1
Freescale Semiconductor
PTIH1
—
0
1
1
DDRH0
PTIH0
—
0
0
0