EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 28

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Logic Array Blocks
Figure 2–2. Stratix LAB Structure
2–4
Stratix Device Handbook, Volume 1
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Local Interconnect
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, M512 RAM blocks,
M4K RAM blocks, or DSP blocks from the left and right can also drive an
LAB’s local interconnect through the direct link connection. The direct
link connection feature minimizes the use of row and column
interconnects, providing higher performance and flexibility. Each LE can
drive 30 other LEs through fast local and direct link interconnects.
Figure 2–3
LAB
shows the direct link connection.
Three-Sided Architecture—Local
Interconnect is Driven from Either Side by
Columns & LABs, & from Above by Rows
Row Interconnects of
Variable Speed & Length
Column Interconnects of
Variable Speed & Length
Altera Corporation
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
July 2005