EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 647

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
The Ethernet PHY (layer 1 of the OSI model) connects the media (optical
or copper) to the MAC (layer 2). The Ethernet architecture further divides
the PHY (layer 1) into a PMD sublayer, a PMA sublayer, and a PCS. For
example, optical transceivers are PMD sublayers. The PMA converts the
data between the PMD sublayer and the PCS sublayer. The PCS is made
up of coding (e.g., 8b/10b, 64b/66b) and serializer or multiplexing
functions.
how Altera implements certain blocks and interfaces.
10-Gigabit Ethernet has three different implementations for the PHY:
10GBASE-X, 10GBASE-R, and 10GBASE-W. The 10GBASE-X
implementation is a PHY that supports the XAUI interface. The XAUI
interface used in conjunction with the XGMII extender sublayer (XGXS)
allows more separation in distance between the MAC and PHY.
10GBASE-X PCS uses four lanes of 8b/10b coded data at a rate of
3.125 Gbps. 10GBASE-X is a wide wave division multiplexing (WWDM)
LAN PHY. 10GBASE-R and 10GBASE-W are serial LAN PHYs and serial
WAN PHYs, respectively. Unlike 10GBASE-X, 10GBASE-R and
10GBASE-W implementations have a XSBI interface and are described in
more detail in the following section.
Implementing 10-Gigabit Ethernet Using Stratix & Stratix GX Devices
Figure 8–2
shows the components of 10-Gigabit Ethernet and
Stratix Device Handbook, Volume 2
8–3