EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 485
EP1S80B956C7N
Manufacturer Part Number
EP1S80B956C7N
Description
IC STRATIX FPGA 80K LE 956-BGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F484I6N.pdf
(864 pages)
Specifications of EP1S80B956C7N
Number Of Logic Elements/cells
79040
Number Of Labs/clbs
7904
Total Ram Bits
7427520
Number Of I /o
683
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
956-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Figure 5–8. High-Speed 1-to-1 Transmitter Clock Output
Note to
(1)
Using SERDES
to Implement
DDR
Altera Corporation
July 2005
This figure does not show additional circuitry for clock or data manipulation.
Figure
Logic Array
Stratix
5–8:
Some designs require a 2-to-1 data-to-clock ratio. These systems are
usually based on Rapid I/O, SPI-4 Phase 2 (POS_PHY Level 4), or
HyperTransport interfaces, and support various data rates. Stratix
devices meet this requirement for such applications by providing a
variable clock division factor. The SERDES clock division factor is set to 2
for double data rate (DDR).
An additional differential channel (as described in
Output” on page
transmitter clock output signal with half the frequency of the data.
For example, when a system is required to transmit 6.4 Gbps with a
2-to-1 clock-to-data ratio, program the SERDES with eight high-speed
channels running at 800 Mbps each. When you set the output clock
division factor (2 for this example), the Quartus II software automatically
assigns a ninth channel as the transmitter clock output. You can edge- or
center-align the transmitter clock by selecting the default PLL phase or
selecting the negative-edge transmitter clock output. On the receiver side,
the clock signal is connected to the receiver PLL's clock.
The multiplication factor W is also calculated automatically. The data rate
divides by the input clock frequency to calculate the W factor. The
deserialization factor (J) may be 4, 7, 8, or 10.
Transmitter Circuit
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD0
PD1
PLL (1)
Fast
Register
Parallel
TXLOADEN
× W
5–10) is automatically configured to produce the
PD9
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
High-Speed Differential I/O Interfaces in Stratix Devices
Register
Serial
Stratix Device Handbook, Volume 2
Inverter
“Transmitter Clock
TXOUT+
TXOUT−
5–13
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