EP1S80B956C7N Altera, EP1S80B956C7N Datasheet - Page 313

• Manufacturer Part Number: EP1S80B956C7N
• Description: IC STRATIX FPGA 80K LE 956-BGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S80B956C7N

• Number Of Logic Elements/cells: 79040
• Number Of Labs/clbs: 7904
• Total Ram Bits: 7427520
• Number Of I /o: 683
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 956-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Altera Corporation
July 2005
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Clock multiplication and division
Phase shift
Clock switchover
PLL reconfiguration
Programmable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Number of feedback clock inputs
Table 1–3. Stratix & Stratix GX PLL Features
For enhanced PLLs, m, n, range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty
cycle. With a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512.
For fast PLLs, m, n, and post-scale counters range from 1 to 32.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
For degree increments, Stratix and Stratix GX devices can shift all output frequencies in increments of at least 45 .
Smaller degree increments are possible depending on the frequency and divide parameters.
PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL. On Stratix
GX devices, PLLs 3, 4, 9, and 10 are not available for general-purpose use.
Every Stratix and Stratix GX device has two enhanced PLLs (PLLs 5 and 6) with either eight single-ended outputs
or four differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1S80, EP1S60, EP1S40 (PLL
11 and 12 not supported for F780 package), and EP1SGX40 devices each have one single-ended output.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
Every Stratix and Stratix GX device has two enhanced PLLs with one single-ended or differential external feedback
input per PLL.
Table
Feature
1–3:
Table 1–3
Stratix GX devices.
Down to 156.25-ps increments (3),
Four differential/eight singled-ended
m/(n × post-scale counter)
shows the enhanced and fast PLL features in Stratix and
or one single-ended
Enhanced PLL
2
v
v
v
v
v
6
(8)
General-Purpose PLLs in Stratix & Stratix GX Devices
(6)
(1)
(4)
Stratix Device Handbook, Volume 2
Down to 125-ps increments (3),
m/(post-scale counter)
Fast PLL
3
v
(7)
(5)
(2)
(4)
1–3